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Recent content by Emest

  1. E

    [SOLVED] How To Delay 100ms From One Output To Other Output In Vhdl

    Hi, may i know how have you done the delay and the case statement? i am facing the same problem like u had before. can u send me the coding? Thanks for your big big help. :wink:
  2. E

    M-file Matlab, System Generator and Xilinx Spartan 6 FPGA LX9 Microboard

    Hi there, Im new here. Lately, I am now doing my final year project using Matlab, System Generator and Xilinx Spartan 6 FPGA LX9 Microboard. In my project, I want to convert m-file to vhdl code in system generator and then program the vhdl code into the Spartan 6 FPGA LX9 Microboard. By the...
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