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C and Verilog
If you ask such kind of question, I think you do some algorithm research in hardware design instead of the pure software designer.
We always use c for modelling algorithms of hardware while use verilog for detailed hardware implementation. In this case verilog in the lower level...
generally speaking VHDL dumping data is in bin or hex mode which can not recognized by matlab
my method is dump in bin mode and use matlab function 1)'fscanf' to read to a vector 2)'bin2num' change bin to number that matlab can recognize then youcan use that vector as you wish
Re: Fpga and asic
Ya!
we are searching for common model for FPGA and ASIC.
Every time we change FPGA to ASIC it will take time. SO this time we just write the RTL model for the use of FPGA and ASIC use 'define function. So that we can use only one RTL code for both.
DVBV-H also, considering FFT number DVB-H includes 2k,4k,8k mode while 802.11a only 64-point FFT core and wimax 256 point
802.11a power is lower than 50mw and DVB-H derives from DVB-T while uses timing slicing only can down to 50mw if DVB-T core naked it will consumes more than 300 mw.
DVB-H...
matched filter matlab
Actually it is a squart raised cosine fir filter but I want to design it with good performance and less coeffiecient in Matlab I used firrcos but it's output is not so satisfactory
systemc dpi pli
Could anybody tell me about the difference and prospect of systemC and systemVerilog. It seems that systemC is supported by Cadence and SystemVerilog by Synopsys. and both are created for system and RTL and verification.
sdf annotation
HI,all
after my synthesis, there are no timing violations in the design.
Then I get sdf file and use sdf_annotate() in netlist simulation using ncverilog.
If the design has no sdf back annotation, the simulation result is correct
otherwise when I add sdf_annotate with sdf...
How a beginner starts?
previously I was an digital IC designer. But I want to do some application work from now on. especially in embedded systems field. Can predecessors give me some advice for the beginning. I think good starts is one half of success.
Book?
Forum?
anything will be appreciated~~~
In my experience, if I meet high fanout net:
During synthesis set_dont_touch_network and set_false_path to it.
all the work will be done in Layout tool:there are special command for high fan-out net just as CTS
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