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Recent content by Elias.xie

  1. E

    dual core testing problem

    In our SOC, there are 2 cores. In core exposed mode, we want to test dual core at the same time with the same pattern for single core. Is anyone who has this experiment? Thanks.
  2. E

    What is the most popular simulator for HDL?

    Who has the modelsim study material, pls send to me, thanks. elias.xie(at).gmail.com
  3. E

    H.264 Decoder IP core

    Need! elias.xie(at)gmail.com
  4. E

    Pre-Layout Verification

    Yes, if you do sdf-annotated simulation, the stimulus should also abey the timing.
  5. E

    What's the file format for GTECH lib

    gtech.db GTECH is just the format of the database synopsys uses, I think that's impossible to see that, that must be encrypted when it is saved.
  6. E

    why area after insert scan chains is smaller compile -scan?

    What two areas do you mean? The one after "compile -scan" vs "insert scan"?
  7. E

    Detailed info about set up & hold

    set up & hold Any basic digital design book can give you the answer.
  8. E

    Can D-Algorithm be applied at higher level than gates?

    Re: Problem on D-Algorithm Yes, but you must build the rules of your own primitive, that's a lot work.
  9. E

    DFT help: sharing scan in

    Are you sure you want to do this? Four scan-in pin share one pin means compressed ATPG, does your ATPG tool supports this?
  10. E

    how to do DFT with black box IP

    That's ok, you can do it, but you should make sure this connection should only really exists when chip in scan test mode.
  11. E

    Hold time problem with Verilog netlist

    hold time problem That's the point! If without reset, it also can work, then you must handle it, I think.
  12. E

    How to increase the length of each scan chain in DFT?

    DFT help Another facets that can low your test coverage are: 1. generated clock logic 2. generated reset logic You should bypass them by test mode signal
  13. E

    How to dump fsdb waveform in vhdl using ncsim of cadence

    fsdb waveform Thanks a lot.
  14. E

    How to dump waveform in vhdl using ncsim of cadence

    Thanks a lot.
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