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sata ip core
Hi,
Can anybody advise the price of SATA IP Core?
For example:
- transport & link layer core (FPGA & ASIC)
- SATA PHY core
Thank in advance
Elektrom
fpga sata core
If low cost systems, you can use SATA<->IDE bridge chip. In this case, you can use Spartan or Cyclone devices for PATA interface, let SATA interface handle by bridge chip.
As far as i known, there are 2 bridge chip that can support both SATA-I/II Host & Device mode
1) Marvell...
Re: HDD interface problem
Are you trying this way?
1) Write Sector count register = 1
2) Write LBA Address [23:0] = 1
3) Write Device head register = 0xA0
4) Write command register = Read sector command code
5) Read status register and wait until data ready bit is set
6) Loop read data register...
virtex-5 sata
VirtexII Pro can not support OOB signaling. It can't use for SATA PHY.
Virtex4FX can't pass SATA Compliant test.
Virtex5LXT and Virtex5SXT are only devices that fully complaint with SATA1/2.
library auk_ddr_user_lib not found.
Hope example this script can help you to compile for DDR2 IP in ModelSim. Please Try to compile all file to correct library.
_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/
# Library mapping
vlib work
vmap work work
vlib...
sata phy chip
I'm looking for SATA I/II PHY Chip that can be use with FPGA such as spartan3 or Cyclone device. I found only 2 chip.
1) TRC3002 from TaraCom (**broken link removed**)
2) Sil3012 from Silicon Image, but it seems obsolete
Can you guys recomend me other Chip?
THX,
Elektrom
Re: RFID
https://ww1.microchip.com/downloads/en/devicedoc/21299e.pdf
It's all about RFID technology from Microchip.
- RFID Basic
- Device datasheet
- Antenna circuit design
- Reference reader design (included circuit)
linux & usb & swab32
We're trying to upgrage from 2.4.19 to 2.6.13. Everything is work fine except frame buffer driver. We uses S1D13506 on our board. The kernel stop booting when load frame buffer driver.
It seems that 2.6.13 for AT91RM9200-DK designed to S1D13806.
Any suggestion to make...
Is it possible to synthesize the post-place & route netlist? Any way to do that? Is it secure to send vhdl/verilog timing model to customer for evaluation propose?
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