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just as a guess, I notice that what you calculate is 310G rad/s and what it tells you is 45 G rad/s. Is it possible that these are not the correct units, i.e. if you divide 310G rad/s by 2*pi you get... 49.3 G Hz/s. Could this be the problem? either way, good luck.
slow response in virtuoso/composer
urm, well, I can't remember: is virtuoso the schematic capture, or is it composer? Well, my previous post is for the schematic capture part of ic5.0 being slow on redhat 7.3. Any help?
slow response in virtuoso
I don't know why but virtuoso is dog slow. especially as i add components. Any one else experience this? It is making it unusable. I have redhat 7.3 and installed the NCSU design kit. Please help a brother out here.
exporting the layout as gds2 in virtuoso
Um, just as a neurotic sidebar: I heard that cadence embeds a code into their gds files that when a foundry "sees" contacts cadence to determine that the person that sent it in is registered.
This is no problem if you actually bought the...
just a thought
weeeell, i was just thinking, about the 50 ohms load thingy... if its the input to the chip you can just put the 50 ohms in series on the outside of the chip (with a nice 1% resistor). If it is leaving the chip, then you can do the same. If it is inside the chip, between blocks...
vco simulation netlist
I agree. Imagine that the transistor is an nfet, and its drain is going above the supply voltage. Well, except for breakdown, this isn't a problem. This happens at different voltages depending on the process, but in, oh lets say .15u TSMC digital CMOS your digital 1.2v...
hspice vco
I used to think this was weird also, but now I look at it like this:
the inductor/capacitor form a tank circuit... and it is very literally that, a tank that stores. This is what allows it to get above the supply voltage, storage. So lets say that you store some amount during one...
hsim shmapesim
Hmmm... the age old debate... hsim or powermill. Interestingly enough I was a big hsim lover for no other aparent reason than it was something new. Painful experience has shown me that although both have annoying shortcomings, Powermill's I can overcome, Hsim's I cannot...
divide-by-3 schematic
umm, if you want you can use two flip-flops connected like so:
node f----| D QB | ----- | D Q | ---- node f
with the clock not shown. This gives a divide by three. But the duty cycle is not 50%. If your pll uses a pfd (edge triggered) this isn't a problem. But...
1 tran+1res
Ok, I just tried it out, and it works fine at 20Mhz (given my transistor, hehe sbc35)
You can just use one transistor and one resistor (like you said). I don't know what you mean by common base configuration, but using a common source is what I did.
(1v->5v supply)|...
i hear your pain. But let me rejoin with this:
1) in several months, Cadence is going to come out with a package (for the analog-mixed signal/layout side) that displays everything in Unix, but actually runs the core( spectre) on a linux machine of your choice.
2) The previous is a prelude to a...
if your looking at it with an oscilloscope why did you mention an FFT? an fft is for discrete time stuff (i.e. sampled). If you want the real solution, its called.... pll! wahoo! you can use one and do clock recovery. Now your having fun. depends on how large the noise is relative to your...
why use fft use to separate the noise
hehe, depends on were the noise lives. If the noise is only additive white noise, then you could use a limiter on your data before using the fft (for instance the data coming in should be between -1 volt and +1 volt, but because of noise is between -1+-.2...
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