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Hi,
I need your knowledge in Synopsys-SAE custom designer environment. I have a schematic and simulations running without problems but I'm trying to include in my output variables through SAE environment parameters like Vdd, transistor width, temperature, etc. I want a simple value to be...
Hello community,
I have a question about adding models when trying to set up an MC simulation. I will be clear enough in what i'm doing:
1| I have my Verilog-A model working with no problems in DC and transient simulations. I've understood that I can use the following line of code in Verilog-A...
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