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Hi all,
I am designing a operational amplifier and using negative feedback in my application,
So V1=V2=Constant voltage, the input voltage is fixed most of the time.
Since input is fixed, I can control the OP consuming current by adjusting input MOS. Can I remove current reference stage as...
Hi all,
I am designing a constant current reference generated by bandgap voltage.
The equation are IREF=VBG/R(poly)
but check with the foundry model , the R variation is 20% in TT-SS corner.
How to reduce the resistor variation effect or make a compensation ?
Thank you in...
LDO pass transistor layout floorplan
Hi all,
I am designing a LDO as second power for a loading block.
The pass transistor is very large for supplying high current.
and also the loading block is very wide.
For the layout floorplan,
Should I distribute the pass transistor to surround the...
I am designing a 10uA contant current as reference current.
I have designed a bandgap reference voltage of 1.2V. In order to generate 10uA constant current, I use a feedback OP drive PMOS to pass 1.2V voltage to 120k resistor. The resistor 120k is too large to be implemented in CMOS process...
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