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Recent content by Eiffel.Z

  1. E

    How and where can I master to use Modelsim6?

    You also can use the Debussy associate with Modelsim to simulate. Debussy can trace the signal, I think it will be more efficient.
  2. E

    Issues with refresh period and burst length in SDRAM controller design

    Re: SDRAM controller Although I have not completely understand the truth of the SDRAM, but from your replies,I have learned more new things.Thank you.
  3. E

    Issues with refresh period and burst length in SDRAM controller design

    Re: SDRAM controller Hi cooljack I have some questions wanted to consult with you. You said that send 4K instruction per 64ms, whether it have to average the time for per refresh instruction? or during the first 40ms I send 4K instruction,and rest 24ms none? another question: if I set burst...
  4. E

    Issues with refresh period and burst length in SDRAM controller design

    Re: SDRAM controller I use the Verilog HDL I don't know how to set the parameter of time. such as refresh time, self-refresh time, lenth and so on.
  5. E

    Issues with refresh period and burst length in SDRAM controller design

    Hi friends I am a newbie in FPGA. now I need to design the SDRAM controller to control the SDRAM w/r (Samsung K4S641632H) 64Mbit. I have some problems to ask you help me. I refer to the datasheet, using the 50M clk Q1: 64ms refresh period (4K cycle) . I don't know the meaning exactly. How I set...
  6. E

    Help me write a CRC16-CCITT core in VHDL

    Re: help in crc Hi, friend. You said you need the CRC16-CCITT. CRC-CCITT=X16+X12+X5+1 is almostly in the HDLC area. I have the HDLC communication code for you
  7. E

    CPU @ RTL Design - Verilog (with complete documentation)

    verilog documentation and2 yahootew3000 Hi, brother. I have a question when I simulate your code given to me. My tools is QII 5.0, and the RAM ipcore transfer result is not the same as your document mentioned. When read RAM, the Data of RAM may be appear at the next edge of the clock, there are...
  8. E

    CPU @ RTL Design - Verilog (with complete documentation)

    simple cpu verilog yahootew3000 excuse me, I have no enough point to download the files. so can you mail these files to me? Thank you very much! E-mail: yikoulian2001@126.com best regards Eiffel
  9. E

    Use of functions,procedures in vhdl

    function in vhdl Well, I talk about my opinion I think all of the Designer wanted the Code simple and understandable. so when we use C language we all want short the code and compress the program. But we design hardware language not the same as C.the terminal aim is convert VHDL to real...
  10. E

    about radix-2 verilog code

    I need to, if somebody have pls send it to me. TKS E-mail: yikoulian2001@126.com
  11. E

    The Schematic input in QII problem

    it's done, TKS
  12. E

    The Schematic input in QII problem

    Hi, Now I design the module_A, define the output[15:0] Data_reg then I design the 2 module, RAM0, and RAM1. I want to give Data_reg[15:8] to RAM1 and Data_reg[7:0] to RAM0. I use the Schematic design. but I cant separate the Data_reg[15:0] by the wires. How can I do?
  13. E

    Is there anybody used the Modelsim to simulate?

    Kanags Thank you for your help, now it can work :P
  14. E

    Is there anybody used the Modelsim to simulate?

    Now I have a question, how to simulate the Altera's Code by Modelsim e.g: IP core and QII lib and so on! TKS!
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