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Recent content by eggzhang

  1. E

    Which way is better to simulate ADC power: RMS or Integrate?

    Hi, saro_k_82, I can't quite understand the second setence of your reply. What do you mean about the "close-in decaps."? In my case, it is still in schematic simulation step. Thanks.
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    How to define the rise&fall time of clock in simulation?

    Question just as the subject. There is a saying regarding this question: The setting of the rise and fall time of clock is arbitrary, as long as your circuit can work with that setting. And the sharper the rising of the clock, will consume more power and add more harmonics to your circuit...
  3. E

    Which way is better to simulate ADC power: RMS or Integrate?

    adc power rms I'm designing a ADC, and want to get the power consumption from Cadence. I'm confused by two sayings: one is based on Vdd*Irms, as supply voltage is constant, while current is various, so making use of the RMS function in Cadence to get the Irms, then get the power; another is...
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    low power comparator design for SAR ADC

    designing a sar adc resolution is moderate, 8 or 9 bits. sample rate is also moderate, around 100KSPS. Only tough requirement is power, aiming to achieving nanowatt level.
  5. E

    low power comparator design for SAR ADC

    low power nanowatt comparator It seems I ask this question without first referring on the board. After searching, I read some paper from others' recommendation. Latch comparator seems a better choice over conditional 2-stage amp. I plan to try two topologies, one is preamp with latch and the...
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    low power comparator design for SAR ADC

    low power comparator Can anyone suggest how to design a comparator for SAR ADC, aiming to achieve ultra-low power but with moderate speed?
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