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Recent content by EEPuppyPuppy

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    Unwanted Voltage Drop for Memory Cell (Similar to SRAM) Design by Using CMOS

    Hi, I am designing a build-in calculation ternary memory cell, which has a structure containing two 6T-SRAM-like circuits as well as some other parts for calculation purposes. And I have a bit-line voltage drop problem which I do not want and also do not know why the drop happens. Like SRAM...
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    [HSpice] Question about HSpice Simulation of Similar SRAM Column/Network

    Hi, Hope anyone could help me. About the circuit: I am working on a circuit which is similar to SRAM but more complex, but it performs kinds of the same way. The basic storage unit (or call it circuit) has write-line, read-line, and bit-line. During writing process: Write-line is ON and...
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    SRAM RC Extraction Simulation

    Re: SRAM RC Extraction Simulation Does NOT Match Schematic Simulation Hi, really appreciate your response. The structure is more close to a SRAM, so the bits are not stored as charge on a capacitor but within a couple-of-inverter loop. I am going to check each parasitic resistance and see...
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    SRAM RC Extraction Simulation

    SRAM RC Extraction Simulation Does NOT Match Schematic Simulation Hi, really hope someone could help me. About the circuit" I am doing an in-memory calculation structure very similar to SRAM which has both write and read. The writing process writes data into the structure; the reading process...
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    Innovus Command Questions

    As a beginner to VSLI design, I am using and learning Innovus these days and have two questions. Hope someone could help me. 1) set_db. The user manual has some sample flows with codes. It usually contains 'set_db' commands to set values for some attributes (the manual calls it database...
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    Innovus CTS .tcl Script Qustions

    Thank you for your previous suggestions. I was looking at the manual, trying to understand it and modifying it fits the test circuit I am working on. By using the commands from the 'Quick Start Example' section (I am using the 18.1 version) and modify it, I could get something without errors...
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    Innovus CTS .tcl Script Qustions

    Hi, thank you for your response. I have searched ccopt_design -ckSpec in google but did not find anything useful. However, I did find another post which contains the conversation between you and another person. In that post you suggest him to use setCTSMode -engine ccopt set_ccopt_property...
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    .sdc file into Innovus WARN and ERROR

    Hi, NotSam. Thank you for your response. Since when I use the command 'setOpCond' it reports the error: **ERROR: (IMPSYC-6137): Command 'setOpCond' is obsolete as the software moves to using Multi-Mode/Multi-Corner (MMMC) architecture for design import. Operating conditions must be set using...
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    .sdc file into Innovus WARN and ERROR

    I was trying to do P&R with Innovus by using the output files from Synopsys. There are several files generated from Synopsys that are needed to be input into Innovus. One of them is the .sdc file which is generated with the command write_sdc However, when the .vew file which is used for mmmc...
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    Innovus CTS .tcl Script Qustions

    We moved from Encounter to Innovus and I am trying to modify the .tcl script which was used for Encounter. The script for Encounter is: clockDesign \ -specFile Clock.ctstch \ -outDir $rpt_dir/clock_report \ -fixedInstBeforeCTS The script above could not be run by Innovus and reported...
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    [Verilog] Asynchronous Reset

    Thanks for your response. Do you mean that during the simulation, 'always @' will compile first and the if loop will compile after that? So while the simulator reaches the line 'if (reset == 1'b1)', the 'posedge reset' has been checked and reset has rised up to 1 already. Therefore, if I want...
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    [Verilog] Asynchronous Reset

    module asyn_reset(clk,reset,a,c); input clk; input reset; input a; output c; wire clk; wire reset; wire a; reg c; always @ (posedge clk or posedge reset) if ( reset == 1'b1) begin c <= 0; end else begin c <= a; end endmodule Above is...
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    Innovus routing and floorplanning with analog components netlist generation

    I have used Virtuoso to do the sketchmatic and layout of my oscillator and other components using TSMC 65nm CMOS transistors. Now I am trying to put my components and any other TSMC 65nm components together to build a large circuit for tapeout. So I need Innovus to do the physical design. It...
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    How to get a TSMC 65nm 10M Ohm Resistor

    Can anyone who has experience with TSMC 65nm technique let me know that how I can create a 10,000,000 Ohm resistor? I went through the PDK and realized that those resistors are way smaller. (There is no way that I connect hundreds of resistors together to get the resistance I want since the area...
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    [HSpice & Cadence] How to find MOSFET Minimum Size from a Library?

    My bad. Already deleted it. :-(
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