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Recent content by EEcrazy

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    ESD protection diodes/SCR layout

    Thanks. I don't believe it is a GGNMOS, there are no poly gates anywhere near ESD protection. That N well also extends under the bond pad itself, but not quite all the way. Would not it just form a large area nwell to substrate diode? Here is what it looks like, both p+ fingers and p+ guard ring...
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    ESD protection diodes/SCR layout

    Does this layout for finger ESD protection diode make any sense? What is the reason for adding n-well right under the n+ contacts? Or may be I have p&n backwards, so its actually SCR? Thx!
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    AMS toolkit violates its own design rules

    How come a standard cell from AMS 0.35um toolkit - vert10 significantly violates design rules, e.g. NTUB to NDIFF should be 1.2um min and it is only 0.55um? NTUB enclosure by PDIF is even worse - 0.45um instead of required 1.2um. Is there something special about those parasitic BJTs I don't know?
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    BG06 bangap from AMS standard cell library

    Anyone has schematics or GDS layout for the BG06 bangap reference? Its a standard cell from AMS hit-kit.
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    CMOS Fabrication process in 80s and 90s

    Is anyone aware of a complete detailed description of the older commercial CMOS manufacturing processes, something between 1um to 2um node? There a lot of simplified process flows out there, and each of them appears to skip different steps. So I could not find an exact answer on some of the...

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