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Recent content by ecikin

  1. E

    Synchronous vs Asynchronous design

    cant download it
  2. E

    How to Synch. two Diff clock.

    shift the CLK_INV50KHZ by a delay of 1/4 of the ON time of CLK_50KHZ?
  3. E

    best book for RISC arch

    i can not find it
  4. E

    Does modelsim support systemverilog simulation now?

    modelsim questa simulator download questasim6.2
  5. E

    The relation between assertions and Formal Verification

    SVA Assertions can not be synthesized
  6. E

    full-duplex Asynchronous serial link - what is it?

    RS232 serial link Rx and Tx simultaneity
  7. E

    RS232C or RS485 for a thousand feet long network

    Question on RS232C you can use RS485
  8. E

    about bus functional modeling

    where is BFM pdf ?
  9. E

    AMBA.........what is this..........what does this do........

    it is very Flexibility
  10. E

    RISC Processor design

    please share cpu code on forum
  11. E

    Free CPU List + website link

    Free CPU List OpenRISC 1000is very good
  12. E

    How to calculate the depth of FIFO and what are the designs contraints for it?

    Depth of FIFO Fifo size = Size to be buffered = B - B * Frd / (Fwr* Idle_cycle _rd ),How to calculate "B"?
  13. E

    Looking for an IC with single flipflop

    single flipflop is it a common FF?
  14. E

    system verilog verification environment

    vmming a systemverilog you can read AVM
  15. E

    How does the buffer reduce delay ?

    Buffer Rabaey's book is very good
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