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Recent content by ecasha

  1. E

    duty cycle calculation

    why? we cant calculate for the combinational loops?
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    duty cycle calculation

    yeah,it was asked in interview queston
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    duty cycle calculation

    How to calculate duty cycle for this combinational logic shown in figure.I know it results in a combinational loop.But I am not getting how to calculate the Duty cycle for this.Please help out.
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    WARNING: NgdBuild:486 in Xilinx

    WARNING:NgdBuild:486 in xilinx I am getting this warning: WARNING: NgdBuild:486 - Attribute "INIT_FILE" is not allowed on symbol "U0/I_YES_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V5.U_CS_B RAM_CASCADE_V5/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B18KGT0.u_ramb16/U_RAMB16" of type...
  5. E

    [SOLVED] verilog code for addition of contents in the memory

    Then how do I write code. Actually, I want to calculate a number of one's in every 4 locations of memory. i.e from 0 to 3 then 4 to 7.
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    [SOLVED] verilog code for addition of contents in the memory

    module opr(clock,di,dread,adr,in1,sum1,cmct); input clock; input [0:5] di; reg [3:0] pn1; input [3:0] in1; output [0:5] dread; input [1:0] adr; reg [3:0] k; output [5:0]sum1; reg [5:0]sum1; output [3:0] cmct; reg [3:0] cmct; integer i,j; reg [0:5] ram1[0:3]; reg en=1; initial begin for (i=0...
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    [moved] MATLAB,Xilinx ISE inteface

    I have written codes in Xilinx and MATLAB.I want to send data from Xilinx to MATLAB and run code in MATLAB with values from Xilinx.How do I do this?
  8. E

    MATLAB, MATLAB simulink, or Xilinx; which is the best one?

    MATLAB simulink ,Xilinx which is best one? what is Matlab Simulink software? what is the difference between Xilinx, Matlab, Matlab Simulink software? I read Simulink is used for testing and validation. Is it hardware testing?
  9. E

    storing values in array

    Another module's 6 outputs, i am sending it to this array.These output values should be stored based on SLT line.like in the first case, 6 outputs are stored in first 6 locations in the second case in next 6 locations.But in the secong case when slt =01 out1-6 are storing in first 6 locations...
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    storing values in array

    Hi, I wrote code for storing output values in an array.There are 6 outputs.For different cases, 6 outputs are to be stored in consecutive locations without altering previous values.Like in the first case 6 outputs are stored in first 6 locations in the second case in nex 6 locations. I have...
  11. E

    [SOLVED] [moved] synthesis error RTL schematic

    Re: synthesis error RTL schematic No compilation errors.It gives the simulation results.
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    [SOLVED] [moved] synthesis error RTL schematic

    Hey guys,I am trying to view RTL schematic but its showing unexpected error. No errors are there in the code & 6 warnings HDLCompiler:1127:Assignment to c5 ignored, since the identifier is never used. Whenever I try to view RTL schematic its showing the error and it terminates.What are the...
  13. E

    code for counter such that it should count for every 2 positive edges of clock

    Is it not correct use frequency divider?
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    code for counter such that it should count for every 2 positive edges of clock

    How to write verilog code such that output values should change for every 2 clock cycles? I have written code for counter,it is changing/counting for every posedge of clock.I want, it should count after 2 posedge clock .How do i write code? always @ (posedge clk) begin if (rst) d<= 0...
  15. E

    verilog code to automatically activate the outputs of demultiplexer

    Hey,I have written verilog code for the 1:2 demux,I want to activate the outputs one after the other without giving select inputs manually.When I run it ,its showing the only f2 output.I want to see both outputs i.e first when select =0 and select=1 one after the other.How to rectify it...
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