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Recent content by dzosgornik

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    AWS EC2 FPGA amazon cloud computing

    Every FPGA retargeting is a tough process, but I guess that if you use standard interfaces to DRAM/PCIe (AXI busses e.g.), then this process will be much easier.
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    AWS EC2 FPGA amazon cloud computing

    What is your purpose? Software to Hardware interaction isn't specific. If you target high performance analysis / CNNs / image and video processing / generally all kinds of co-processing, then AWS is good for you. If you want to develop for "real" FPGAs, just buy a development board.
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    BRAM based FIFO buffer for matrix multiplication

    Hi maha_66, the most simple solution is to use predefined modules/macros: See https://www.xilinx.com/support/documentation/sw_manuals/xilinx2018_2/ug953-vivado-7series-libraries.pdf In your case the XPM_FIFO_SYNC macro would be ideal, or maybe XPM_FIFO_AXIS in case you need some kind of...
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    Constraining synchronous reset as false path?

    Hello everyone, I'm working with the Cyclone 10 GX and want to attach multiple modules to the EMIF (External Memory Interface) Controller. This controller has a reset output, which I would like to use as a global reset signal, since all modules are attached to the DRAM with their own DMAs. All...
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    Pipeline stages regs

    In my understanding additional register stages for BRAMs are required if your instance requires lots of BRAM blocks and thus wiring to the processing logic would be spread across a wide range, requiring some pipeline registers to increase maximum operating frequency. In most cases you won't...
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    AXI4 to AXI Stream conversion for Ultrascale PCIe EP support

    I'm still not sure, what purpose your design will have - but here is my generic recommendation: Use the DMA/PCIe combo (https://www.xilinx.com/support/documentation/ip_documentation/xdma/v4_0/pg195-pcie-dma.pdf) if you want to have a simple PCIe to AXI-MM adapter. I used it in my accelerator...
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    AXI4 to AXI Stream conversion for Ultrascale PCIe EP support

    What is your use case? Both IPs are able to move data from memory mapped to streaming (and vice versa) - the AXI-DMA requires a master in the design, which configures the DMA by writing to registers, the DataMover has a streaming interface for control. In any case we need more information...
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    Is the "Gaisler method" of writing "structured VHDL" popular?

    I'm fresh from university, and I learned both styles: 2-process at first (with focus on state machine style), and after that everyone just used the 1-process style for everything. For simple designs, this approach is legitimate (single process, sequential flow, ...), but as soon as I started to...

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