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Recent content by DZC

  1. DZC

    Is there any issue with this circuit?

    To correct the duty cycle of a 5GHz clock, I come up with the attached circuit. For 5GHz clock, R=10K and C=100fF. It works almost perfect according to simulation. But I just kind of worried, is there any issue associate with this scheme I have ignored?
  2. DZC

    Where is the EDA ebooks upload/download section?

    haven't login EDAboard and I found it missing? Is it still exist in this forum?
  3. DZC

    small and large signal difference

    To my understanding, large signal is kind of transfer function when you apply a slow enough signal small signal is around some specific point such large signal transfer function
  4. DZC

    question about threshold voltage in 90nm technology

    I doubt what you've checked is corner related paprameter? Do a simple .OP or .DC in hsipce and check the log file to get the real vth Good luck!
  5. DZC

    How to model a SERDES analog PHY with verilog?

    Hey ,guys, I got a task to built a verilog HDL (not veriloga) model for a SERDES AFE. This model will be provided for our digital guys to simulate. Anybody ever do this job? Would you plz show me the general procedure?
  6. DZC

    how to collect 3.3v to 5v inside chip?

    3.3v to 5v ic I'm afraid you might took pranam77 by mistake. I think what he suggest is to use 5V vdd for analog part and then shift down to supply 3.3 digital. Another solution might use charge pump to boost vdd, but that will be costly and the 5V supply noise will be terrible if not proper...
  7. DZC

    Is 1k ohm for an on-chip resistor a large value?

    on chip resistance Generally speaking, there's high poly resistor (r***_sab) available. Their sheet resistor are about 1Know Ohm/square. Then hundreds of K Ohm will be reasonable. All in all, you have to check the sheet resistance of all the resistors available first.
  8. DZC

    Problem with annotating in Spectre?

    spectre annotate My environment is IC5.10.41. I found it difficult to control the annotate status of the schematic. Occasionally it displays the right annotations as my choice, but most often it just annotate the Node voltage and can't be reset... Any good ideas?
  9. DZC

    Choosing specification and designing flash type ADC

    flash adc design flash seems not a hot topic now except that you've got some brilliant idea already. Good luck !
  10. DZC

    How to modeling a SATA cable, plz?

    sata cable simulation I have the SATA RX and TX circuitm, and now I'd like to have a far end loop back test simulation. But I have no idea how to model the channel. Any suggestion?
  11. DZC

    How to implement a PLL lock detector?

    pll lock detector Is there any common used method?
  12. DZC

    About single loop multibit delta-sigma modulators

    matlab fast bitget Hi,rfsystem,but could show me some example. I do know some single loop sigma delta modulator use MSBs to feedback and throw away LSBs. And when compare with sigma delta ADC, the feedback signal is the MSB(Δ)?! Do you mean in MASH? thanks a lot!
  13. DZC

    How can I deal with 3rd HD in a 2nd SigmaDelta Modulator,plz

    I am designing a second order sigma_delta modulator for audio application. The input frequency is 8kHz and the sampling rate is 1MHz. The design target is 16bit but he simulated 3rd distortion of the SDM is as high as -54dB. The slew rate of the first OTA designed to be 20V/µs. What might is...

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