Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Dwaipayan

Recent content by Dwaipayan

D
Can anyone help me in how to translate a Matlab code to verilog.

I have a matlab code which I need to convert to verilog can anyone help me how to do it.
- Dwaipayan
- Thread
- Jul 12, 2011
- Replies: 1
- Forum: PLD, SPLD, GAL, CPLD, FPGA Design
D
Verilog array of registers synthesis problem

I have a code where I have an array of registers mainreg having sixteen registers, I want to consider the first block of 8 registers from 0 - 7 from these 8 i want to separate 2 pairs of register arrays having 4 registers each and then again do the same thing from the next block of 8 registers...
- Dwaipayan
- Post #8
- Jul 6, 2011
- Forum: PLD, SPLD, GAL, CPLD, FPGA Design
D
Verilog array of registers synthesis problem

Thanks it is working. I would like to know something say in this design I am specifying the register inputs that is they are fixed and thus mentioned through the 'assign' clause. What is the way if I want the register contents to be dynamic i.e, I want the data_str contents to be dynamic, how...
- Dwaipayan
- Post #6
- Jul 5, 2011
- Forum: PLD, SPLD, GAL, CPLD, FPGA Design
D
Verilog array of registers synthesis problem

@ADI : Can we use non-blocking in the combinational block?? ---------- Post added at 12:08 ---------- Previous post was at 12:00 ---------- @FVM : I have done this but there is a different problem. Actually I need two register blocks like this the first register block (data_str0) and the...
- Dwaipayan
- Post #4
- Jul 5, 2011
- Forum: PLD, SPLD, GAL, CPLD, FPGA Design
D
Verilog array of registers synthesis problem

I need to add the contents of four registers in an array I have written a code but on synthesizing it creates latches : `timescale 1ns / 100ps module regblock0 (sum, Clk, nReset, nReady); input Clk, nReset, nReady; output [15:0] sum; reg [15:0] temp1, temp2; reg [15:0] sum; wire Clk; wire...
- Dwaipayan
- Thread
- Jul 5, 2011
- Replies: 7
- Forum: PLD, SPLD, GAL, CPLD, FPGA Design
D
array initialization on separate file in verilog

I have tried something similar but the data dat i am passing through the define clause appears as 'zzzzzz' when simulated in modelsim please help
- Dwaipayan
- Post #16
- Jul 4, 2011
- Forum: PLD, SPLD, GAL, CPLD, FPGA Design

Part and Inventory Search

Dwaipayan

Welcome to EDAboard.com

Recent content by Dwaipayan

Can anyone help me in how to translate a Matlab code to verilog.

Verilog array of registers synthesis problem

Verilog array of registers synthesis problem

Verilog array of registers synthesis problem

Verilog array of registers synthesis problem

array initialization on separate file in verilog

Part and Inventory Search

Connect with us

Online statistics

Forum statistics