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Recent content by dustin76

  1. D

    UMC 0.18um erc error

    I guess the BJT you used in BGR is PNP, so the NW of the base is connected to VSS. But NW should be connected to VDD generally so is highlighted by ERC. Some of the ERC errors are just remind you to confirm the physical connections are what you want and could be waived.
  2. D

    P-Well Layout in TSMC 65nm

    DNW is like a buried layer and need NW to provide potential. So you should draw DNW without a hole then draw NW like a guard ring and connect to the highest potential. As for PW, I never used TSMC process before, but PW should be operated layer generally means you need not to draw it manually.

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