Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
[URL="https://stackoverflow.com/questions/61818155"]Just posted the answer over at Stack Overflow]
I haven't proved that this works yet, but it seems to compile without errors:
tri [7:0] tri_DQ;
assign tri_DQ = DQ;
assign tri_DQ = ddr4_if.DQ;
assign DQ = tri_DQ;
assign...
Recently downloaded a memory model for DDR4 memory from micron's website and found that they have converted their models into System Verilog Interfaces.
I'm ok with that... however, I still need to put a wrapper around it to make it work with mixed VHDL/Verilog-2001 simulation. I'm not...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
