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Thank KlausST very much. Your comment is really good for me after my chip is fabricated.
Currently, I just wonder how to simulate ENOB, INL/DNL of TDC. So do you have any suggestion for simulation?
I've just finished design TDC. I check each output code in very small period of time to find out it is correct or not, surely that is not the way, but I don't know what's the best way to evaluate the performance of my design.
Could you please give me any suggestions about evaluate...
I simulated my circuit using Hspice and I got the error "Error: Internal Error: code  in new analysis."
The problem is I run 2 simulation, one-ckt1 can be finished and another-ckt2 got that error, and I tried to simulate ckt2 again, but it still was error. I really don't...
I got the simulation result based on the book:"Analysis and Design of Analog Integrated Circuit" 4th Edition. Also, as you see the definition of ICMR, it seems does not relate to Vout, just only Vin (if that, you do not need to plot Vout in graph). But ICMR is affected by output swing...
Actually, kickback noise can make offset to your circuit as u mentioned.
To remove it, you can read some techniques in some following papers (i think they are the best for your circuit):
1. Kickback Noise Reduction Techniques for CMOS Latched Comparators - Pedro M. Figueiredo.
I have already learned 6.002x Circuits and Electronics online course offered by MIT. Here is the link:
**broken link removed**
I think this course is pretty nice to motivate your learning process.
Hope this help!
I read the paper:" A 10-bit 50-MS/s SAR ADC with a monotonic capacitor switching procedure" and i do not understand how the authors get the average energy in picture (a):
At the first conversion, why the energy is C*Vref^2 and 5*C*Vref^2, and so on...:?:
Any ones can point me about...
As far as i know, W and L of differential input pair will be consider by some following specifications:
1. W/L is large to increasing gm, so it means that gain also increases.
2. L need to be small, and W to be large to minimize device offset: Vos is ~ 1/(W*L)
Normally, depend on the...
I have already designed LDO, and as far as i know, the tutorial: Low drop-out(LDO) linear regulators: design considerations and trends for high power supply rejection (PSR), the author is: Edgar Sanchez - TMU is very helpful.
Another useful document is the book: "Analog IC Design...
To calculate the gain of this circuit, the first thing you must do is fixing your circuit as some guys mentioned above. And then, you draw the small signal equivalent circuit, you will that the gain is:
Av = gm2*(r02//r04)*gm6*(r06//r07)
After that you can build a test-bench...