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Recent content by dtn_me

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    HDL Softwares Modelsim, ISE.....

    Good idea is always to start with simulations. Once you are sure that there are no compilation errors, and your design is performing as expected, then move on to synthesis. Industry follows the similar flow : Design --> Simulation --> Synthesis --> Backend flow Modelsim is from Mentor. Latest...
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    which verification methodology to be used??

    Yes. You can say that the methodology we select depends upon tool or vendor. If we use Synopsys VCS, we may have to choose VMM. If we go with Mentor, OVM is preferred.
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    What is a "callback" in Systemverilog?

    what is callback in systemverilog We may have to create a verification environment that can be used for all the tests. Test program should be able to inject new code without modifying original classes. Any change in the transaction(like injecting errors, inserting delays, synchronizing this...
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    which verification methodology to be used??

    Recent trend has System Verilog as verification language to increase the portability and reuse of TB features. For communication between various layers of TB, OVM methodology is preferred.
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    Data buffer for PCIe physical layer verification

    PCIe Phy Hi I am doing PCIe physical layer verification. For Gen1 and Gen2, PCIe transmits 20 bit data and receives 16 bit data. I am in the process of bulding up a test bench environment for this. I am actually preparing an expected data buffer. This is 16 bit buffer. Need to take 16 bits...
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    Looking for project that uses OCP-IP protocol

    Re: OCP-IP protocol We used Verilog for OCP models and USB OTG controller. Regards DTN
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    What does inter frame gap in ethernet contain?

    Re: ethernet For 10MBPS slot time is 512 bits, min Inter Packet Gap(IPG) is 9.6us & Min Frame size is 64 bytes For 100MBPS slot time is 512 bits, min Inter Packet Gap(IPG) is 0.96us & Min Frame size is 64 bytes For 1000MBPS slot time is 512 Bytes, min Inter Packet Gap(IPG) is 0.096us & Min...
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    Role of DMA in USB????

    The input and output devices and their drivers expect to be able to put/get data in response to a hardware interrupt from the DMA controller when their transducer has processed one service period of data. The DMA controller can move a single sample between the device and the host buffer at a...
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    Looking for project that uses OCP-IP protocol

    Re: OCP-IP protocol We used OCP as an interface for our USB OTG. You can get details about OCP from https://www.ocpip.org/
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    verification to design engg

    Verification to Design is easier. But and RTL guy trying to change to verification is a bit difficult. Time depends on ur competency.
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    gate level simulation issue

    Initialize all the inputs to proper value
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    What are the job requirements for a front-end ASIC engineer?

    Re: ASIC engg Basic things u need to know include 1. Basic Digital Electronics 2. Verilog/VHDL programming basics(Basic theory) 3. What is ASIC & FPGA ? 4. Tools used in full front end flow. But dont try to understand much about tools if u want to be in front end vlsi. But, if u want to be on...
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    Why we are using only D Flip-Flop in IC design?

    Re: D Flip-Flop D Flipflop is completely scannable(Controllable & Testable).
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    What's the best reference to learn System Verilog?

    Please let me know best source to learn System Verilog.

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