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Good idea is always to start with simulations. Once you are sure that there are no compilation errors, and your design is performing as expected, then move on to synthesis.
Industry follows the similar flow : Design --> Simulation --> Synthesis --> Backend flow
Modelsim is from Mentor. Latest...
what is callback in systemverilog
We may have to create a verification environment that can be used for all the tests. Test program should be able to inject new code without modifying original classes. Any change in the transaction(like injecting errors, inserting delays, synchronizing this...
I am doing PCIe physical layer verification. For Gen1 and Gen2, PCIe transmits 20 bit data and receives 16 bit data. I am in the process of bulding up a test bench environment for this.
I am actually preparing an expected data buffer. This is 16 bit buffer. Need to take 16 bits...
For 10MBPS slot time is 512 bits, min Inter Packet Gap(IPG) is 9.6us & Min Frame size is 64 bytes
For 100MBPS slot time is 512 bits, min Inter Packet Gap(IPG) is 0.96us & Min Frame size is 64 bytes
For 1000MBPS slot time is 512 Bytes, min Inter Packet Gap(IPG) is 0.096us & Min...
The input and output devices and their drivers expect to be able to put/get data in response to a hardware interrupt from the DMA controller when their transducer has processed one service period of data. The DMA controller can move a single sample between the device and the host buffer at a...
Re: ASIC engg
Basic things u need to know include
1. Basic Digital Electronics
2. Verilog/VHDL programming basics(Basic theory)
3. What is ASIC & FPGA ?
4. Tools used in full front end flow.
But dont try to understand much about tools if u want to be in front end vlsi. But, if u want to be on...