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Hello,
I am trying to design a small device to operate on 868/915MHz band. Since size and cost are top priorities we decided to design the PCB as small as possible and also embed a small circular loop antenna on the device. Now, one of the problems of the loop antenna is the high-Q behavior it...
Dear all,
I am designing a PCB with AT86RF215 RF transceiver and I want to use an external TCXO. The datasheet states that to use a TCXO de input should be clipped sine wave and the peak-to-peak voltage should be between 600mV and 1600mV. My problem is that I want to connect this TCXO to 2...
Thank you very much. But when the substrate thickness is very small, where is the power lost/dissipated since it is not radiated? In the conductor, substrate?
Dear all,
I would like to clarify a question that has been haunting me lately: what is the relation between substrate thickness and antenna radiation efficiency for a patch antenna designed in a substrate with Dk = 6?
During my simulations I have observed that if I increase the substrate...
Hi,
I am planning to design patch antennas to operate on 868MHz and 915MHz (only one frequency at the time). To achieve a good trade-off between BW (spec. 12 MHz), size and cost I am planning to explore some high Dk substrates (or ceramic) with a yet-to-be-specified thickness (assuming that it...
Thank you very much. In order not to create a new thread, I will ask here another question hoping you guys can clarify me :)
During the simulation of a patch antenna I am viewing both the Vector Electric Field and surface J. The surface J current models the charges movement and density around...
After a quick calculation I saw that the conditions that HFSS example indicates (Inner radius = 0.7 mm, Outer radius = 1.6 mm and er = 1 ) lead to a 50 Ohm coax cable :). However, I have still not found answers for the remaining questions.. Again, thank you for your time.
Hello all,
I am fairly new to EM and Antenna modelling and simulation, therefore, I beg a pardon on some of the following non-sense questions that I might inquire.
Recently I have been playing around with HFSS in order to simulate a patch antenna. The patch antenna is fed by a coax cable. To...
[Square Patch Antenna w/ Dual Feed] Asymmetric Radiation Pattern
Hello everyone,
I am currently simulating a square patch with dual probe feed, as you can see on the following image:
The distance from the centre that I chosen for both probe feeds is the same. Afterwards, I used two wave...
CMOS PA + Output Matching Network Simulation
Greetings,
I am currently simulating a CMOS Power Amplifier. To complete the schematic level simulations, I need to capture all the effects of bondwire + external inductors parasitics. This way, I decided to mount the external MNT in ADS. However...
Well, when simulating the design, if I set a running clock frequency higher than the one I used to synthesize the design (during place and route and etc) I get a lot of warnings indicating setup/hold time violations, so, I would assume that the timing checks are properly in use..
But any more...
Hi guys,
I am performing the last timing checks to my placed and routed design. Using Innovus I wrote the SDF and .v verilog file, which I then used in NCSim. Although everything went as expected, when compiling the testbench (where I issue the sdf_annotate command), I get the following output...
Actually I have not. This is because I do not know yet which block/cell/IO will be interfacing my chip from the outside world.
But any recommendations regarding that?
Well, this is quite similar to my situation. However, I get such warnings only regarding IO cells and not the sub-sequent std cells.
Thank you very much for your time.
With kind regards.
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