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Recent content by DSD

  1. D

    DC synthesis result violates design rules constraint

    Hi, all If DC synthesis result violates design rules constraint(max_capacitance, max_fanout) but meets timing requirtment, how does this affect the later design process and the chip's function and timing? How to set the appropriate design rules constraint on a given design? Thanks & best regards
  2. D

    naming style for identifiers in verilog HDL

    There are two familiar naming styles for identifiers (signal names, port names, module names etc) in verilog HDL. 1. Use lower case letters for all identifiers, for example, rx_flow. 2. Mix lower case letters and upper case letters for all identifiers, for example, RxFlow. Which style do you...
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    How to get xilinx fpga technology library files(.db) for DC?

    hi,I want to use synopsys DC to synthesize my design targeting Xilinx FPGA,but I don't have xilinx fpga technology library files. Are these files free of charge and can be download from Inernet? Can I generate these files using Library Compiler or other tools? :?: Thanks!
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