Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Re: drop out voltage in LDO
Here is the link to the LDO thesis:
Current Efficient, Low Voltage, Low Dropout Regulators
by Gabriel A. Rincón-Mora
Ph.D. Thesis in G. I. T. 1996
Volume: 198 pages
**broken link removed**
how to simulate the offset of comparator
Please check:
Principles of Data Conversion System Design byRazavi Bezhad
There are detail explanations about the comparator. Get the book at:
**broken link removed**
You can find the detail analysis of L for MOS at Ch1 and Ch2 of the following book:
Analog Design Essentials
Author: Willy M.C. Sansen
The books is available at:
**broken link removed**
Re: guard rings
Try this book
The art of analog layout, by Ray Alan Hastings
There is a systematic explanation for Guard Ring
you can get the book at:
**broken link removed**
degeneration resistor
Pleaes read p.p.60 (3.2.5: CS Stage with Source degeneration) for details
Design of Analog CMOS Integrated Circuits
Author: Behzad Razavi
You can get the book at:
**broken link removed**
Re: can someone recommend parpers about low voltag LDO desig
Study and Design of Low Drop-Out (LDO) Regulators
Authors: Gabriel Alfonso Rincon-Mora & Phillip Allen
**broken link removed**
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.