Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Dear FvM, I think now I see what you mean. Correct me if I am wrong.
You mean, to have lets say 8 laches, and drive each one with clock shifted by +45 degree. And to rout signal-in to this latch chain?
Because what I understood first was, to have 8 FFs, and trigger them by incoming signal, and...
This means to take high enougth clock freq?
OK, but in first case ), how to deal with transient values of phase shifted clocks? I mean - there is probability that signal will come with rising( or falling) edge of one of the clocks (probably more, 2-4 depends on number of phase shifted clocks)...
Input clock is 40 MHz. With PLL it can be multiplied up to 350 MHz.
Added after 1 minutes:
Can you please describe in more details "phase shifted channels" method?
Dear ALL,
I have to measure time intervals with precision of 750 ns with FPGA.
Is there any known methods of doing this?
Will be gratefull for any ideas.
Thanks.
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
