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Hi. all~
It is about stb simulation and AC simulation of Specter.
There is buffer composed of 2 stage OTA.
- DC gain 60dB
- 0dB Freq.=1Meg
- PM=60'
If these two buffers are composed as shown in Fig.1 and frequency stability is evaluated, the loop gain using STB method is 0dB. However...
Your answer is right.
I absolutely agree your opion.
Thank you very much^^
But i mean that method of Fig.1 can not reflect fast response of GREEN path of Fig.2.
So how can i evaluate include this phenonmenon.
As you told me, I search LvW's article.
Thank you very much. FvM^^
When evaluating the frequency stability of a two-stage OP-AMP using a Miller capacitor, 'stb' simulation was used for the input stage.
Fig1 is an example of the conventional method of determining the loop gain and phase by the 'stb' simulation.
Since the 'stb' instance can be connected...
I post it because of the frequency stability evaluation method in spectre(or hspice).
The example in the figure below is an example of the method I already know.
In the Fig.1 , it is simulated by putting 'stb' in the main loop (BLUE) on the output of -A2.
Also, for the stability of the local...
Thanks for the useful teaching.
https://www.edaboard.com/threads/how-this-peaking-can-cause-the-stability-of-the-system.66585/
According to #12 of this link, the stability can be seen by the Q value.
I wonder how I can get a solution with this.
I only have a circuit, and finding the transfer...
Thank you for your teaching.
After designing the system as above, stability is verified by tran simulation in all PVTs. As with time-efficient design by verifying stability with 'lstb of hspice', I am curious about how to verify the stability of transients.
(In the control system, stability...
Thank you for your important teaching.
But I still have questions.
After designing the system as above, stability is verified by tran simulation in all PVTs. As with time-efficient design by verifying stability with 'lstb of hspice', I am curious about how to verify the stability of transients...
This is the case of a 3 stage amp with negative feedback.
The output is a source follower, so amplification is done twice.
If you look at the method of finding the loop gain using lstb in hspice, the phase margin is 90'.
However, there is gain peaking at frequencies after the unit gain...
Hello Friends Im new to the whole Power Management and Analog Design sphere .
I have a question. If anyone knows, please tell me.
As a general LDO, the output PASS Tr. is PMOS.
To improve PSR+, the open loop gain of PASS Tr can be reduced. How to reduce the open loop gain of the last stage...
Hspice DC simulation result is unusual and error.
The input is shown below, and the output is shown in the figure.
Do you know the cause and solution?
Sandwork version is 2013.03-SP1,
Hspice version is Hspice_L-2016.06-SP2.
Thanks in advance.
******** Input ***************************
.param...
I use spectre.
But I don't know how to check with specter.
How can I check the breakdown voltage (VGS, VDS, VGD, VGB) of 12V asymmetry MOS with Specter?
Please teach me.
Is there a way to check the breakdown voltage of the MOSFET in Hspice (Hspice_L-2016.06-SP2)?
12V asymmetry MOS, I want to check the breakdown voltage of VGS, VDS, VGD, VGB.
(I am using the Globalfoundaries 130nm BCD process.)
Thanks in advance.
I need a high performance integrator.
And I want to check 'Stability of the integrator block'.
So I designed it like the figure, and assigned it as the STB instance of SPECTRE at the place labeled VAC and simulated it.
Loop gain and phase margin are shown in the figure.
The area marked in red...
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