Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Recent content by drasta

  1. D

    What's the purpose and application of a guard ring

    Re: Guard Ring leelamadhav is right for NWELL you use nmoat guard ring connected to the VDD and for PWELL you use pmoat connected to the GND. It is usually to lower noise on board ant isolate the device usually analog.
  2. D

    which one is more matching for these two layouts?

    It is true than on first currents flow in the same direction but if you shift mask I dont see how first can be better because than M21 and M22 will have smaller D than S or vice versa but on the figure 2 shifting will afect the same D and S. So be carefull.
  3. D

    Assura LVS error: PSUB_StampErromFloat

    Re: assura lvs error You have several substrats that are not connected together but some of them maybe floating you should connect them, check wells and conntacts and them metal lines.
  4. D

    Connecting ground and substrate in deep n-well process?

    Re: Ground and Substrate You will nedd analog and digital groun separately or some filtring circuitry between analog and digital groun and than you can connect supstrate with grounds.
  5. D

    please introduce or supply a book on analog ic design

    You have a lot of books on analog design and layout in download e-books section, I recommend Allen and Razavi books.
  6. D

    Dummy capacitor for MiMCap

    drumy cap I think that you can for sure use half of W around with very good characteristics.
  7. D

    cadence vs tanner L-edit

    I used both and think that CADENCE is afcourse better more user frendly, when you master it and most important all big foundaries use cadence and have models and scripts adjusted for it.
  8. D

    Simulating a potentometer in Pspice

    I think that with .PARAM and .STEP PARAM you can sweep wide range and see what happends, you dont need some special model.
  9. D

    What is the future for CMOS Analog IC Designers ?

    I think ADC and DAC's will always be interesting for analog designers and also verilog or vhdl or avhdl is good to know because of its wide use but also power supllies and band gap references.
  10. D

    Bandwidth and Gain Bandwidth

    Usually it means large GBW because you need high gain in large BW.
  11. D

    Help me select an output buffer

    Re: output buffer? I think that you can design it because you know specifications for output voltage and current, and maybe you can find some digital gates for this but +/-13 volts is a bit high for standard digital gates.
  12. D

    question about metal filling

    all layers and all part in ic layout must be connected to some potential. It's bad to have floating metal or well or any other component everithing must be connected.
  13. D

    Where do the harmonics come from in OpAmps?

    Re: Harmonics Nonlinearity can develop from narrow bandwidth of amplifier and also unstability.
  14. D

    Question on DAC for WLAN application

    wht is msps MSPS is mega samples per second and its similar to MHz sampling frequency. Sampling frequency in DAC exists because it has its frequency of conversion and digital signal can be oversampled or interpolated and filtered in order to get better performances easear filtering and bigger SNR.
  15. D

    Need advice on using Gate Oxide Capacitor

    Re: Gate Oxide Capacitor I think that you should connect source and drain together as one electrode and gate is the other and well must be connected (Nwell to a high potential).

Part and Inventory Search

Back
Top