Dr.Che

Extensive experience as a qualified semiconductor researcher with success in practical implementation of newly-developed semiconductor power devices. Highly skilled semiconductor engineer and researcher, with experience in Scientific researches in Semiconductor Physics and Technology, 15 scientific publications, namely:

Technology interface to GLOBALFOUNDRIES (65G), TSMC (65LP, 40LP).
Analog ESD protection development for TSMC 40LP technology.
Foundry PCM data analysis.
High experience with layout design and optimization, process flow.
Simulation experience with HSPICE, TCAD tools and environments, Unix design systems experience.
ASIC design, clock/power distribution and analysis, RC extraction, timing analysis.
IC layout verification (DRC)
EDA tools for MEMS/NEMS design and analysis.
MOS Gated Power Devices.
STI isolation, Trench refill, Chemical Mechanical Planarization processes.

Implemented Projects:
Detectors Design and manufacturing: Humidity Sensor (Integrated Capacitor), Pressure Sensor (Bulk Silicon orientation (110)
Trench Gate with Carrier Storage (CS) layer IGBT simulation and optimization.
ChemFET and enzyme - protein sensitive FET
Design and manufacturing BIB (Blocked Impurity Band) Photodetector for the 12-16 micron wavelength, 64x64 array, flip chip mounting with multiplexor, cooled T=10 K.
MOS controlled thyristor (2500V, 50 A)
Press Pack HV-IGBT (4500V, 40 –1000A)
Solar Cells made with multisilicon wafers, 11.5% efficiency
Avalanche Photodiode simulation (3D Single Event Upset) and optimization
Semiconductor device models implemented with VHDL simulator
Simulation and design submicron SOI MOSFET
SJ MOSFET Devices (CoolMOS), special development – SJ MOSFET Avalanche Ruggedness, various die edge termination structures.
Junction Termination Extension Variation Lateral Doping (JTE VLD), own theoretical results in design optimization.