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Thanks for the replies! I was re-reading the datasheet and wanted to ask if complex mode could do what I needed?
There are 10 inputs;
1 output (with it's own output logic)
and 4 logic expressions each with >8 product terms (as described above).
Thanks...
So, I would need 2 OLMCs for each expression like the one above? So, I would need 8 OLMCs in total for 4 complex expressions?
But I only have 3 spare output 'pins' for the extra OLMCs and I think that not all OLMCs can have feedback paths (if I've read the datasheet correctly) -...
I did think of using the feedback paths of the other pins but there aren't enough! Can't see how else to split the expression...
Unfortunately this is the device I have to use.
Hi. I'm trying to a program a G16V8 using WinCUPL. I have 4 quite complex logic expressions - each with >8 product terms (which is the max allowed for this device). Is there a mode/CUPL technique that allows this to be implemented or is it just plain impossible?!
By the way I only have a couple...
OK, sorry for the incomplete info.
num is a std_logic_vector.
The error I get when I 'implement' (mapping stage) is
ERROR:Place:1108 - A clock IOB / BUFGMUX clock component pair have been found
that are not placed at an optimal clock IOB / BUFGMUX site pair. The clock
IOB component...
Hii -
My first post here. I am trying to store a value on a button press:
num <= switches(7 downto 0) when button = '1';
Now, when I synthesise this it warns of latches on 'num' but that's what I want (to store the value of the switches when the button is pressed). When I try to implement I...
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