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Hello again.
I've made some changes in my design but still something seems strange to me.
In these two images, I just changed the data depth from 1024 to 512. but in the 0 frame, my values changes. Is it normal?
That's what I was looking for it!!
Yes, I was wrong about the concepts of software and VHDL design, but I just wanted to explain what am I trying to do. Even with all of this, your explanation was complete and helpful. Finally someone exactly pointed at my problem.
As I figured, I should...
My design is not fully combinantial. As I replied to Kaus, it is a computational core, but the software that run on this core is a combinantial circuit.
Yeah, that's my main problem.
I'll work on it. Is there any tutorial or something that explains how to do that? I've never done such before.
Actually, it's a computational core that some simulation algorithms run on this core and for now, it's combinantial.
Because the value of my counter register shows that the execution time was about 8 seconds! and I'm sure that it's impossible.
Do you mean trigger ports? If so, trigger ports are my main outputs and the counter register that counts clock cycles.
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You mean that these...
As I figured, by large data you mean that it takes few seconds to complete the operation, so that I could measure the execution time manually with an external timer, right?
Dear Tricky,
No. I don't have anything that changes my execution time, but the main purpose of my work is to measure the speed-up gained from running on FPGA because it consumes a lot of time running on CPU.
By simulation, I think the clock cycles may differ from execution on FPGA (or maybe...
Hello everybody
I'm trying to measure the exact execution time for my VHDL design. The problem is, I don't have a digital oscilloscope to see how many clocks spent for generating the final output. I added a counter to my design for counting the clock cycles, so that by multiplying the clock...
Thank you for your complete explanation dear @ads-ee .
Now I've got the concept. It seems that it's kind of designing a simple specific-task processor, and of course it has the complexities as you mentioned. Beside the challenges you mentioned, I have to deal with feedback loops and it makes it...
That's what I was talking about!
I've done some works with Xilinx FPGAs and somehow I'm familiar with VHDL. In this particular case, I don't understand how to convert the algorithm steps to digital blocks, it's really confusing. For instance, you can code the graph nodes easily with linked list...
Well, You are right. But I think we deviated from the problem, so I re-explain it.
You know, some algorithms are very time consuming. It takes months or even years to run on a PC and it's because of the serial nature of the CPU. So, we have to accelerate these algorithms by running them on GPU...
I didn't ask someone to complete the work for me ! All I want is to get help and know how to start to implement this framework.
I think you didn't get what I meant, I want to run a C program on FPGA instead of CPU, not converting the program.
By converting the C program to HDL there is no need...
As you mentioned, I have the algorithm written in C language. In this algorithm we have a large graph needed to be traversed, so it takes long time to perform. Because of this matter, I want to accelerate the algorithm by running on FPGA.
In fact, I want to implement a platform on FPGA for...
Hello everybody,
I'm going to implement a graph traversal algorithm on FPGA so that it takes a design as its input and traverse the graph from the beginning point to the end on the FPGA.
In this design every node has some information to be processed during the traversal.
How should I start...
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