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How to do the ams simulation , using verilog + verilogA ?
Now My top cell is verilog file, in which the analog sub-module is instantiated.
1. The analog sub-module is SPICE netlist.
I can run the ams simulation.
The amsd block is :
include "./source/ana_cell.spi" (...
How to do the ams simulation , using verilog + verilogA ?
Now My top cell is verilog file, in which the analog sub-module is instantiated.
1. The analog sub-module is SPICE netlist.
I can run the ams simulation.
The amsd block is :
include "./source/ana_cell.spi" (...
i have used IC5141 schematic composer editor to draw a circuit, using a library.
Now i want to change the new library, so the library name & N/PMOS symbol name are different from the previous those.
i want not to re-draw the same circuit. How will I do ?
I encounter a problem when using cadence 614 .
i have a sub-circuit named SNV.cir & i have its spectre netlist. then i create a symbol using cadence symbol editor. i use this symbol to draw my top circuit using cadence schematic editor. when i want to simulate my circuit, the cadence fail to...
My SPICE netlist is named bufk.sp
Only 2 inverts are included. i use the command :
spp -convert bufk.sp bufk.scs .
but No result generated.
then how will i do the conversion ?
My SPICE netlist is like :
.GLOBAL VSS vddh
***
.SUBCKT HINVA I ZN
MM15 ZN I VDDH vddh MP5 L=0.72U W=3.6U AS=1.8P...
Hi, i need the spectre netlist of " device noise simulation of sigma delta modulators "
From here, "http://www.designers-guide.org/Analysis/" , the matlab script will be got. but the spectre netlist is missed.
i want to re-simulate the 2nd order sigma delta converter using specterRF simulator...
i need some helps!
i use IC5141 USR6 schematic editor and PDK symbols from TSMC.
For P/NMOS transistor, I want to remove the bulk terminal since almost all MOS transistors' bulk terminal is tied with source supply VDD/VSS. so the circuit look simply if all MOS bulk terminal is removed.
i want...
i need some helps!
i use IC5141 USR6 schematic editor and PDK symbols from TSMC.
For P/NMOS transistor, I want to remove the bulk terminal since almost all MOS transistors' bulk terminal is tied with source supply VDD/VSS. so the circuit look simply if all MOS bulk terminal is removed.
i want to...
i have found the reason:
The error is cause by my MMSIM61.
If i use ic5141 usr6 spectre rf simulator, the simulation result is right.
but if i use mmsim61-base spectre rf simulator, the result is wrong. but the PSS can convergence successfully.
should i re-install my mmsim61 again ?
I have read this document : https://www.designers-guide.org/Analysis/sc-filters.pdf
I want to re-simulate the example named Track & hold .
This problem confuse me :
If the previous MOS model ( Level-3 model ) is used, the PAC & PXF result is similiar whith that in the paper. but if the my...
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