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laker tech file?
Hi all,
Lately I use laker to edit my gds . But when I "stream in " the file *.gds, *.tf, Laker always reports error"can't map the gds to tf". I don't know what leads to it.
Now I use the tf which is for calibre. So I want to know if I use laker, should I ask for the...
Hi,
When I run DFT, it reports : cann't download the simulation libary
The TCL I write is :
set test_simualition_library $PATH/memory.v
WHAT ERROR lead to the result?
Thank you in advance!
When I use LEDA check my RTL codes, it reports many violations:
1. Flipflop with fixed value data input is detected.
2. Top level output ports is not registered.
I don't why. Please help me fix them. Or tell me some rules when we edit RTL codes to avoid the violations.
Thank you in advance...
lef generator
hi, friends,
For backend design, it needs the format files of .lef. In my design , I choose Charted.35 library. However they don't supply the format files .lef. I need to use Memory Builder to generate LEF file for RAM.
How to use the software Memory Builder ?
or...
hi, everyone!
warning:cell s% is unknown(black box) because funcitonnality for output pin s% is bad or incomplete.
warning:cell s% is constant 0 value.
warning:design 's%' comes before design s% in the link library; s% will be ignored.
warning: port s% cannot be used as a scan port. it has been...
shadow logic in asic
When i used the script " [get_object_name [get_pins U3/O]] " , the design compiler points out the u3 is not in the current design NET. I couln't find the reason.(maybe the question is a little foolish. i am a tyro)
thanks！
set_testability_configuration
In my module design, there are 2 rams & 1 rom. I want to configure them as black boxes. I use shadow logic DFT. the Design Compiler version has 2 modes:XG & DB mode.
XG mode: set_testability_configuration -type observe -clock_signal....
DB mode: set_wrapper_element...
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