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Recent content by donald007

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    What is Verification Plan and Test Plan.........?

    Basically, they means the same thing. Just different word(Verification and test). Verification Plan: It is generate by -reading the spec -extracting function -extracting rule -create "checker" -create "functional coverage" -... You must list all things about verification...
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    SDF Error: Negative Delay ignore and replace by 0

    negative delay in sdf Dear all, I am running post simulation. I got the following message. "SDF Error: Negative Delay ignore and replace by 0" What does this mean? Is it important? Can I ignore it? Thanks, Donald YEH
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    Selecting a domain in clock domain cross

    cross domain clock Hi, I think it can have two kind. First, "register access": you can use two flip-flop to construct a handshake protocal. Second, "continue data exchange" (ex. DMA): you can use asynchronous FIFO.
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    Anyone has Verilog syntax highlighting for gVIM??

    gvim verilog hi hpinmax, You can find it in your gVIM install directory. ex. c:/Program Files/vim/vim71/syntax/verilog.vim
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    How to handle the interrupt processes in AHB?

    AHB & Interrupt AHB bus doesn't handle interrupt. Your system need a "interrupt controller" to monitor interrupt from device. And assert FIQ or IRQ of ARM cpu.
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    fifo pointers - Y only gray code pointers are used ???

    The reason of using gray code is that multi-bit synchronization problems. Only one bit change.
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    Help me design a divide-by-5 sequential circuit with 50% duty cycle.

    divide by 5 Is there another way to do this? Because our PLL may not provide 2f clock in current project. 2f: double frequency
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    what is vera equivalent of always?

    Hi you can try this. fork { while(1) { if(x == 8'h0) a = 1'b1; else a = 1'b0; ... ... } }join none
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    OOPS in System Verilog

    systemverilog profile You can learn basic concept of OOP, then you can start to use SystemVerilog. Try example code is helpful.
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    Does ncverilog support "local variable" in propert

    Hi all, I am trying writing a SVA to check one interface on a IP. But I get a compile error in the line "logic [10:0] v_page_adr;". I use "ncverilog +sv". Do you know ncverilog support "local variable"? Thanks. property p_linkpg; logic [10:0] v_page_adr; @(posedge clk) A |-> B...
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    What does R mean in ncverilog -R?

    I use VCS before. I don't familiar with ncverilog. What does -R mean?
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