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Thanks for the reply!
It's actually GaN-on-SiC - 3 mil substrate thickness, with a <1 um layer of SiN just below the metal layers... so not the lossiest substrate.
The confusing part for me is that stand-alone components and 50 Ohm lines are a much better fit to the PDK models using TML ports...
Hi Everyone,
I'm designing a MMIC PA at ~40 GHz and have noticed that the EM simulation results for my matching networks show VERY different results when switching between TML and TML-zero ports.
I've always been told that TML ports are the best option if they're on the boundary of the...
Ok... definitely definitely try and solder more caps onto the gate and drain lines. It's probably best to use the recommended datasheet capacitors because it will save you time looking for the correct voltage ratings.
If you haven't already, have another look at the small-signal S-parameters...
The decoupling should be ok if you try and use similar capacitor values and types to those in the datasheet circuit.
https://www.wolfspeed.com/downloads/dl/file/id/317/product/117/cgh40010.pdf
In the above datasheet, notice how the gate and drain feeds have 5 or 6 caps in parallel, stepping up...
The gate voltage required for your desired bias point may not be exactly the same as that printed on the datasheet. As an example, if you apply say, exactly -2.4 V to the gate, hoping to get an IDS of 100 mA and you see an IDS of 50 mA or 200 mA, it's because the bias point is slightly...
Hi. Yes, that should be ok. Personally, I would use more attenuation at the output and keep the VNA input level around 0 dBm, because the VNA signals tend to be cleaner between -20 dBm and 0 dBm. The VNA probably won't be able to drive your PA hard enough to make it reach 40 dBm anyway - not...
Many VNAs are rated to about +30 dBm (1 W) input power so you will definitely need an attenuator if you plan to measure the S-parameters under large drive conditions. It would be best to try and keep the output power below +10 dBm for peace of mind.
Generally, it's acceptable to measure...
Hi Everyone... I need your help with what should be an easy question to answer.
I've written some code to design a basic 3rd order charge pump fractional-N PLL based on transfer functions and a simple linear model. Here's where I'm getting confused...
Depending on whose book I use, the...
Hi All,
Please ignore my previous reply - I got myself in a pickle and couldn't make up my mind which frequency step to use.
What I need to know more than anything is, what circuits can I use to achieve the integer division? If my reference, f_ref is 10 MHz and my VCO output range is 690 -...
Thanks for your help. I've got the Razavi book stashed away somewhere so will dig it out and take a look.
Also, the jitter/phase noise/spurs issue is something I'll worry about once I've found a generalised solution.
Is there a test I can do to check whether or not the dual modulus divider is...
Hi Klaus,
Apologies if my description was vague. You're right about finding a general mathematical solution. I've attached a very crude PLL diagram with some arbitrary numbers as an example so please forgive any unrealistic values.
Let's say I want to design a synth whose output, f_VCO, is...
Hi folks,
I'm having trouble finding equations or literature on how to design a suitable frequency divider.
Ignoring the sigma-delta stuff (for now), I want to know how to "hit" every channel in a fractional-N PLL synth. Let's say I know the frequency step (channel spacing), reference...
I had exactly the same problem where the computer suddenly shut down and my project would not open on restart (whereas other projects were fine).
The de_sim.cfg.old file did not exist and the de_sim.cfg file was empty. Writing "PROJECT_VERSION=1000" in the empty file did not save the day...
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