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Depending what kit/process you are utilizing there are usually marker layers that will denote the different sub connections within each sub-block which eventually tie to the one substrate connection at the top level.
Yes ABBA is the first choice but also try to keep the number of fingers on your components even to make dummy transistors identical in X & Y dimensions.
Re: off-grid problem
Easier here is to draw the path then convert to polygon then chamfer the corners.
This goes much faster where you can chamfer the 90 degree angles in one move.
cadence layout xl 2007 segmentation fault
Looking for some help on what the cause is when a Cadence session crashes when using Virtuoso : LE/XL Version 5.10.41_USR6.127.29.
There are 2 types of crashes.
First is while editing in the layout the whole session is killed and closed out. Here you...
Hello,
Just looking for documentations / references & advice to good wiring practices for
Analog Mixed Signal (AMS) Circuitry. IE : patterns/crossovers etc..Thankyou in advance for any help here.
Dave
In Assura LVS form at the bottom click on "Modify av CompareRules" button to open "avCompareRules form. Select "abort onUnboundDevices" from the list and click the "Use in Run" button on. Also make sure the "Abort On Unbound Devices" button is off then click apply. Run LVS next .
Hope this helps...
cadence stream in
You can stream in the gds file in the CIW window under : file > import > stream in.
You may have to specify a layer map table to point to to generate the correct layer purpose pair numbers to see all of the data. Usually if you have a CAD engineer on board to help you line the...
I am looking for a script that can identify where a particular cell is being re-used for other Top Level designs within the same library. Just need to avoid collisions where if a cell being re-used in multiple designs and not being re-named can be qued to see in what other designs this is being...
cadence turbo toolbox
Looking for feedback on the value of this tool. Is there a sacrifice on edit/verification speed that outweighs the benefits.
Please advise. Thankyou
Dave - IC MASK Design
I am referring to Electrical Design/Simulation/Extraction coupled with
layout Design/verification/extraction methodology flow for Silicon Custom AMS
Design within a CADENCE environment !!
Thankyou !!
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