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FPGA Module issues
Hey,
I am pretty new to FPGA. I am confused about the program 'flow' in verilog.. What I want is to have a module with nested modules. Like:
module large( a, b, c, d, out)
multiply (a,b, out1)
multiply (c,d, out2)
out = out1 - out2
multiply(out, d, out)...
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