Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Recent content by Div_01

  1. D

    [SOLVED] Basic addition related (Digital electronics)

    DAC8811 code : library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any...
  2. D

    [SOLVED] Basic addition related (Digital electronics)

    Yes, the sine values are generated in MATLAB and a look up table is generated. And the 1320 is the clock period, which I do not understand how the value was obtained. To create a demodulation clock, should there be a clock divider operation of sorts?
  3. D

    [SOLVED] Basic addition related (Digital electronics)

    Hi, The bits are signed values. It is a delta sigma application. The block diagram of the process is attached here Divya
  4. D

    [SOLVED] Basic addition related (Digital electronics)

    Hi, I have a question regarding addition in digital electronics, quite application specific. 1)Let's say, I have 2 16-bit data coming from DAC and ADC to the demodulator that is 32 bits after multiplying. How many times is addition done to obtain a 40 bit data? 2) What would be the demodulator...
  5. D

    Basic PC to FPGA UART Tx and Rx : Nexys A7

    Thank you for the quick response! Regarding (3), do you happen to know which website I can refer to? As most of the examples I have come across involve generation of sine waves
  6. D

    Basic PC to FPGA UART Tx and Rx : Nexys A7

    Hi everyone. I am currently exploring the Nexys A7 FPGA board. When I was using Nexys2 Spartan 3E board, I was unable to send data from PC through UART. My questions are, 1) How can I establish PC to FPGA connection using UART communication? In the sense, I want to send the data from PC to my...
  7. D

    [SOLVED] Verilog Error

    `timescale 1ns / 1ps `default_nettype none // for SPI MODE 3 module spi_msg #( parameter nrRWregs = 4, parameter nrROregs = 12 ) // nrRWregs + nrROregs should be <= 16 ( input wire sysClk, // FPGA system clock (must be several times faster as SCLK, e.g...

Part and Inventory Search

Back
Top