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Recent content by dirac16

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    ADE XL switch view list for simulating verilog functional code

    Finally I could make AMS simulation up and running thanks to @dominik's great hint! 1637835959 I was thinking on the opposite side actually! I wanted to model my digital blocks using VerilogA because ADE can hopefully handle all-analog blocks. But don't know if that is a good practice.
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    ADE XL switch view list for simulating verilog functional code

    Thanks for the hint. Would you please let me know how to set a mixed mode simulation then? I need to put together many analog, digital and also behavioral Verilog blocks and run mixed signal simulations.
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    ADE XL switch view list for simulating verilog functional code

    I have run into a problem with simulating a verilog code in ADE XL window. Here are what I have done so far: Created a new cellview, cellA, and chose its cell type as Verilog and its cell view as functional under Library myLib. By clicking OK a text editor popped up, then wrote down a simple...
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    Post simulation of back-annotated pnr netlist does not work

    I'm facing a problem with a post-pnr simulation. I know the question has been asked several times out here but I have not found the answer yet. I did post-synthesis with DC compiler, my timing constraints were met and the simulation of the netlist+SDF works as expected. I did PnR with Innovus...
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    Timing analysis accuracy when MMMC definition file not given RC corner

    Thank you. I have just added a qrc file I found for 1p6m_4X1Z0U in my mmmc file. I imported the design and got no errors. But like captables which are defined for specific conditions, should a qrc file be defined for a specific condition too? The qrc file I found had no condition specified, so I...
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    Timing analysis accuracy when MMMC definition file not given RC corner

    Alright. But there is a command setExtractRCMode with an engine option that can be set to 'detailed'. Following this command ExtractRC can be called in each stage of ASIC flow prior to timing analysis. Does that help? 1636994420 Oops, I just found a QRC table that was hidden in the PDKs! As it's...
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    Timing analysis accuracy when MMMC definition file not given RC corner

    Yes it is true. So based on this LEF file given how can I develop my own precise RC values? I have not given any qrc files.
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    Timing analysis accuracy when MMMC definition file not given RC corner

    OK. I am using a particular LEF technology file from tsmc 65 nm process node. In the beginning it has written the following caution: # The LEF technology files included in this directory contain resistance and # capacitance (RC) values for the purpose of timing driven place & route. # Please...
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    Timing analysis accuracy when MMMC definition file not given RC corner

    I want to configure my mmmc definition view file such that only a single mode single corner analysis to be defined. For the current design I have given only technology and standard cell LEF files. In the mmmc browser there is a section called RC corner in which a cap table is required to be...
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    How to tell the sdf_annotate() which delay it has to annotate my design with?

    I have written a tcl file and to the link library added only a fast.db file. Now suppose I include a second db file but this time a slow.db to my tcl file. Now in order to simulate the gate-level netlist with sdf back-annotation delays how should I choose the fast or the slow delay I defined in...
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    Double-delay inverter and its non-linear delay transition

    I have a double-delay inverter chain as shown in the image. The actual purpose of this inverter chain does not matter for the sake of this question. Each double-delay inverter is formed by parallelizing two small and large inverters. The small inverter can be turned off by a gating control...
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    post synthesis simulation methods for power estimation

    I am trying to do my first digital synthesis design using design vision. I have got a question along the way. There are two methods to estimate power consumption to my knowledge: First method comes directly after the synthesis is done; while we are in the Design vision we go to the Attribute...
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    Effective resolution and dynamic range (of ADC)

    No I think ENOB and effective resolution are not the same thing. See https://www.analog.com/media/en/analog-dialogue/volume-40/number-1/articles/adc-input-noise.pdf
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    Effective resolution and dynamic range (of ADC)

    Do effective resolution and dynamic range describe the same thing? Per my understanding, the effective resolution and dynamic range are defined as the ratio of the full-scale input range to the RMS input noise, including both the intrinsic and quantization noise. The only difference I found was...

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