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Re: how to test the "input leakage current" of sch
Hi,
Depending on your level of design (student proj. vs. production design) there are several cases I can think of:
1) Simple Schmitt trigger: Run simulation with input at Vin(min) and Vin(max), measure current through the input voltage...
First, note again that the slew rate is *NOT* symmetric. Therefore, you have a different calculation for the slew rate going high versus the slew rate going low. run some experiments in simulation to get a feel for this.
Second, the load should be the first thing you determine for design of...
I think reza is saying, by unbalanced, that your falling slew rate is limited by the current mirror.
In other words: Your spec is 1V/12.5ns, which equals 80MV/sec.
But with 2mA into a 26pF load (higher with the parasitics), you only get:
2mA/26pF = 77MV/sec.
This will be worse with the...
Hi Fom,
Wowsa! Does that mean you have 200nA for each bjt, or 200nA total for all 30?
If the latter, that means 6.7nA each!!!
Mind if I ask how much variation you see in the bangap voltage output?
thanks!
Here's some thoughts:
1) You need to look for worst case transitions. In a NOR gate, to switch low, worst case is only ONE nmos device pulling low (not two), hence one signal should stay low (while the other rises). If you keep B low, the output sees parasitic capacitance from BOTH pmos...
Hi Incol;
Your analysis is correct; think of it as a bandgap, but instead of applying feedback at the bandgap voltage to keep Vx=Vy, it does a comparison AT THE POINT of Vx=Vy. That comparison latches in the state when VDD is sufficiently high, giving you the "power-on okay" signal.
Note that...
finding floating nodes
Hi gafsos;
HSIM defines a floating node just like Hspice: anything that is not being driven through any device to a power source. These include any MOS transistors with the gate not connected, any capacitor with one side floating, or any stray wires that aren't tied...
what is vt of a transistor
As many definitions of "Vt", there are also as many methods of measuring Vt. The most standard method we use in industry is called Maximum-gm extrapolation. It is good for most practical purposes:
(1) Set Vds = 0.1V (this ensures device is in linear region)
(2)...
The architecture depends entirely on the critical specs of the design. Are you optimizing for speed, power, voltage, or area? Is there temperature sensitivity or variation of the cell current?
One good starting point is the common gate amplifier included in attachment. It's a workhorse for...
The previous replies are correct, it is just ohm's law.
Check your simulation: perhaps you entered a resistor that's too low a value such that the current hits its maximum of the 0.5A source. The schematic as shown should work fine; just make sure you entered it properly, or post it and we'll...
Re: test of bandgap
Arsenal,
You will have to look up in the manual which one has the lowest input leakage current. If you can't find the manual, google the model number and you will likely find it online. Leakage current is definitely a cause of measurement error with regard to bandgaps...
id for gm
Good discussion, hopefully we can have more inputs on this.
My experience is that it is an excellent starting point for circuits; i.e., a good method for feasibility studies, as well as estimations of first pass designs on very new technologies.
For older technologies, it is far...
Hi supercede,
Looking at your opamp netlist, you have Vin+ and Vin- swapped.
Thus when you connect it in your main circuit netlist, you have positive feedback.
Fixing this should clear up a lot of things!
Also, I think what srijesh is referring to is the overdrive voltage of the transistors...
Re: Should channel length be multiple of the minimum of the
Both previous posters are correct: there are no restrictions other than those noted above. However there are some practical considerations:
1) You must double check the grid size that the layout groups work with; increments are...
Hi pseudockb,
I would recommend avoiding these lengths, and perhaps doing everything possible design wise to increase the current bias, even if only in one stage. Alternately you could investigate weak-inversion biasing. If you post some details of the design, we might be able to help...
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