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Hi,
Write Freq=27Mhz and 8 bit data width.
Read Freq=50KHZ and 8 bit data width.
and Depth=(27MHZ X 8)/(50KHZ X 8)=540
Will this is the right way of calculating depth.if not please let me know the right way..
I am using FIFO in I2C bus.
Hi,
I am new to Perl and in text file trying to throw away the repeated line which I felt is OK and rest of the line remain unchanged.so can somebody have some light upon that.
Hi,
I have a Xilinx ML402 board and need to use the USB ports provided to
transfer data at high speed from the board to a PC. There is a Cypress
CY7C67300 on the board.
So how to use the ml402 only as a peripheral to transfer data to the pc.
Is their need to change any of the Cypress USB...
Hi,
I want to implement USB core which need UTMI compatible USB transceiver chip.which board of xilinx having USB transceiver chip.?
As such I am having ML402 Virtex4 Board having USB host and peripheral with Cypress 67300 controller IC.
So My point is that will this IC work as USB transceiver...
Hi,
I am using ML310 virtex 2 pro board in which their is 2 USB port and I want to implement USB core which need UTMI compatible USB transceiver chip.Will this board support transceiver chip.So far I am unable to find in data sheet of Board.
Re: T1/E1 CDR in FPGA
Hi,
I am messed up with is that Suppsose E1 signal is coming from Transmitter which act as input to FPGA and we are doing Deframing of E1 implementaiom in FPGA.Now when E1 signal comes why cant directly we give to FPGA.
2)In CDR bascially its menas we need to synch. the...
Hi,
I am implementing CRC-4 checksum on E1 transmitted data.
--------------------------------------------------------------------------------------------
CRC-4 is structured in a multiframe consisting of 16 frames numbered 0 to 15.The CRC-4 multiframe is then divided into two eight frame...
Hi,
Can somebody guide me which Actel FPGA Family should I select for E1/T1 operates at 2.08 MHZ.I have written code for E1 deframer and now at implementation stage on FPGA.So please guide me above of same.
Regards,
Dinesh
FPGA Implementation Part :I am using Virtex 2 pro and Having E1 Defarmer code using Double Format and My Doubt is E1 signal is Bipolar but how can I give Bipolar E1 signal to Fpga which has I/O standard in monopolar .I am Attaching the E1 bipolar waveform.
Hope so I cleared My Doubt.
Please Provide Assistance on Below E1 :
Synchronization achieved only after receipt of three E1 frames in double frame format.so when synch=1 then only data is valid on the bus.
Its means we start capturing the data from 3rd frame when synch=1 i.e. TS1 to TS15 and TS17 to TS 31 time slots. Am...
Synchronization achieved only after receipt of three E1 frames in double frame format.so when synch=1 then only data is valid on the bus.
Its means we start capturing the data from 3rd frame when synch=1 i.e. TS1 to TS15 and TS17 to TS 31 time slots. Am I thinking right.
Please reply.
My Doubt is in E1 double frame Format Synchronization be achieved only after receipt of three E1 frames .So in Deframing of E1 will first three Frame contain valid data in TS1 to TS15 and TS17 to TS 31.
Regards,
Please clear doubt
1)In E1 Deframing during Framing Synch. of First Three Frame When Synch. Establish after that we start capturing data from TS1 to TS 15 and TS17 to TS31.Its means we need to skip data of First Three Till Synch. achieved.I am Thinking Right if not assist me.
Regards,
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