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Recent content by dilinx

  1. dilinx

    [SOLVED] Suggest me best Video Sync Separator

    Hi all, I am doing a video project where in i need a sync separator. Pls help me with ur valuable suggestions.
  2. dilinx

    initialise the counter with desired value verilog/vhdl

    reset is the best option bcoz it suits all situations......
  3. dilinx

    How do I create a 1 us clk

    its better if u can use DCM or PLL for FPGA implementation, because if u implement clock division module as a counter it will take data path in FPGA (in FPGA clock is given a special care and routed in special paths) and hence chances of timing violation is more.....this (DCM or PLL) will...
  4. dilinx

    single cycle processor mips 32 bit (data memory)verilog

    one thing i can make out is, u missed semicolon for previous statement i.e.
  5. dilinx

    single cycle processor mips 32 bit (data memory)verilog

    About initial bock, this depends on ur implementation.....if u want memory to be initialized on power up, use power-up reset and initialize to known values.....dont use initial.....
  6. dilinx

    single cycle processor mips 32 bit (data memory)verilog

    the example i gave previosly.... modify ur code like this for all "$display" statements..... "//synthesis translate_off" and "//synthesis translate_on" are two constraints used to indicate XST or any other synthesis tool that anything between these two lines should not be synthesized and hence...
  7. dilinx

    single cycle processor mips 32 bit (data memory)verilog

    sorry....yes u are right....change your code accordingly.... besides these, i think there is no synthesis error.....
  8. dilinx

    Xilinx ISE WebPack 9.1i sp 3, gated clock warning

    Re: gated clock warning PLL or DCM, u can costomize them in coregen and instantiate it in your top module (in place of "clkdiv" module)..... for more details about DCM and PLL go through xilinx FPGA user guide..... if u have any doubts let me know.....
  9. dilinx

    single cycle processor mips 32 bit (data memory)verilog

    for all "$display" and "initial" replace with synthesis translate off and on for e.g. //synthesis translate_off $display($time, " rom32 error: unaligned address %d", address); //synthesis translate_on
  10. dilinx

    single cycle processor mips 32 bit (data memory)verilog

    hi funjoke, YES. "$display" is also not syntesizable....if u want it for simulation use sythesis directive "synthesis translate_off" and "synthesis translate_on"
  11. dilinx

    Xilinx ISE WebPack 9.1i sp 3, gated clock warning

    Re: gated clock warning Hi cyboman, By looking at ur design it is clear that "clkdiv" module of ur design will be implemented using LUTs and FFs....that means "clk_out" is going in data path.... To avoid this use DCM or PLL for "clkdiv" module.....
  12. dilinx

    Xilinx ISE WebPack 9.1i sp 3, gated clock warning

    Re: gated clock warning Hi cyboman, The warning message itself tells about problem and solution. In FPGAs in order to avoid timing issues clock routing is given a special care...You cant let clock to go in data path. This will give a warning.... Dont gate the clock, if it is necessary...
  13. dilinx

    Clear my doubt regarding AHB SPLIT and RETRY

    thanx semiconductorman for ur reply.... i have another question..... what is the maximum frequency by which AHB can work and what is the difference between AHB, ASb and AXI?
  14. dilinx

    Clear my doubt regarding AHB SPLIT and RETRY

    Hi all, I'm currently working on AHB slave interface, I have following doubt 1) can a slave give RETRY response to 2 masters at same time? 2) what happens when two slaves (assume A & B) requests a split resume (HSPLITx[15:0]) to the same master?
  15. dilinx

    map report interpretation

    I dont know which FPGA you are referring to.. In virtex5 there are 2 SLICEs in a CLBs and 4 LUTs, 4 FF and other logic per SLICE... Slice Logic Utilization refers to total number of LUTs or FFs used by the design.... Slice Logic Distribution refers to total numbers of SLICEs used..... There may...
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