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i need help understanding this verilog code..
in this code first 2X1 multiplexer is made using gate level model..
then they have used the instance of 2X1 mux to create 4X1 multiplexer..
i dont understand how they have used 2x1 mux in 4x1 generation and then used 2x1 and 4x1 mux to generate...
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