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In my design, I have several clock domains. The standard cell vendor's design rules suggest to use shielding for clock nets with > x MHz, which for me applies to just a single clock.
I can implement shielding for all clocks by defining a custom route_type with -shield_net and specifying it in...
Hi all,
I'm using attribute enum_encoding to define my own encoding for enums in VHDL. However, I cannot get this annotation to work in INCISIVE (15.2). Checking the doc, the only mentions of the attribute I can find are
In the "VHDL Modeling Style Guide for Formal Analysis" ("Currently, only...
I don't know if I'm making progress or heading straight into a dead end:
For single signals where I need to constrain the skew, creating a skew group from the source pin in questions gives messages to suggest that creating a clock tree might be in order. So I create a clock tree instead of a...
It sure does. But not in the way I want it. I certainly do need more control over what's happening.
But how should I specify a skew constraint for a single net? I need to refer to a group of nets for a sensible definition of skew.
digitalo
Hi all,
in our old INNOVUS flow, we used bufferTreeSynthesis to create buffer trees for high fanout nets, e.g. the async. reset.
Now we are in the process of migrating to CCOpt, and I cannot find a suitable alternative. I considered skew groups or H trees, but neither seems to be what we need...
In the input file I have
for( i = 0; i < num_channels; i = i + 1 )
begin : gen_one_channel
channel channel_I(…).
end
After GENUS, I have
channel \gen_one_channel[0].channel_I(…);
channel_1 \gen_one_channel[1].channel_I(…);
channel_2 \gen_one_channel[2].channel_I(…);
But I need
channel...
No, I had not tried this. But is doesn't help anyway. It gets me back to channel, channel_1, channel_2 ….
(I have tried set_db root: .auto_ungroup none).
Hi all,
this has been asked and answered a while back for an older version of RC:
https://www.edaboard.com/showthread.php?t=195042
I have the same problem, but the old solution ported to GENUS no longer works for me. To be more specific:
I have a Verilog module "channel" that has several...
Hi all!
We want to upgrate our flow from purely best-typical-worst view flow to AOCV based. Unfortunately, I cannot find much information on how to generate the tables. I'm using the Cadence ETS suite to simulate them from MC models. The models allow me to specify by how much the models are to...
Synchronizing the reset removal to the clock doesn't help you, when you then distribute the synced signal so slowly that the delay approaches a full clock cycle.
Your tool will tell you when you get into this situation.
Dirk
---------- Post added at 08:53 ---------- Previous post was at 08:50...
Hi all!
I have an ASIC design where I want to implement the classical two-flip-flop reset synchronization. The clock is generated on chip, the reset is an external signal. The FFs have asynchronous set/reset inputs.
Of course, I put the synchronization flip-flops in the same clock domain as...
Yes, I'm all but convinced it is.
I don't get annotation problems for IOPATH specifications or specifications without COND in the SDF. I can force warnings about IOPATH by removing the corresponding line in the Verilog module, so the correct set of modules is picked up. As far as I can tell...
Hi all!
I'm building a standard cell library. Everything is working, but post-P&R digital simulation with SDF backannotation. The most basic IOPATH statements work just fine, but about everything more complex fails.
For example, a DFF with SET input, the SDF contains:
(WIDTH (COND D==1'b0...
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