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Hi every body
I have bellow code:
-- Four-bits divider
library IEEE;
use IEEE.std_logic_1164.all;
entity Divider_nBits is
generic(N : integer :=4);
port ( divisor : in std_logic_vector(N-1 downto 0); -- divisor
dividend : in std_logic_vector(2*N-2 downto 0); --...
Hi
Does any body have complete scripts to estimate power with Prime power ?
I want to use vcd file for power estimation. which files should be used except vcd file?
Hi every body
I have this warning in prime power tool:
warning:The net "reg" in not covered by VCD file
can every body help me for solving it?
why I see this warning? is it important?
Many thanks for your help
I use ordinary transient simulation and vpwl or vpulse voltage source to generate digital sequence. I use tsmc's library. I need to help to design control logic( for reading and writing ). Can you help me in this way? or introduce a reference?
Thanks for your guidance.
I use Cadence tool for simulation. For power measurement I measure average current of supply voltage and multiply it by value of supply voltage. ( P= Vdd * I )
Average current is different in different time intervals. Now I want to know what time interval is suitable...
Hi all,
I am trying to simulate a DRAM cell using Cadence. I create the DRAM cell that consist of a transistor and a capacitor. Large DRAMs are divided into multiple subarrays. There are some wordlines and bitlines in the subarray for controlling write and read mechanism.
I have studied VLSI...
Hi everybody
I want to measure and compare power consumption of digital modules with different architectures. For example some counters with different transistor level structures.
For fairly compare, I must simulate all of them in the same conditions. Can anyone help me about these...
Thanks for your guidance. I don't know how I should split up the chain and force it to implement two inverter chains far apart!
I don't know how I should set constraint!! I guest Synplify tool optimize circuit and remove all buffers and inverters! I should force it to keep all of them but I...
Hi
I need to design a ring oscillator on FPGA. I create it by a chain of inverters and one AND gate for reset oscillation. There is no problem in simulation but when I program FPGA, it doesn't work and I don't know why!!
I use IGLOO Actel FPGA.
Please guide me.
thanks
Hi everybody
Who can help me about Flash*Freeze mode of IGLOO nano Kit?
The Actel IGLOO and ProASIC families of FPGA devices are based on Actel nonvolatile flash technology and single-chip ProASIC3 FPGA architecture.
The Flash*Freeze technology used in IGLOO and ProASIC3L devices enables...
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