Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Ok, I understand.
I didn't understand in your previous post because I was confuse due to what I really know from my specs is the Ibias, not Vbias.
Now, I have understood that I fix Vbias in order to fit that M5 must be bias.
Thank you and excuse me.
Yes I knew the equation that gives the saturation region.
I did the analisys that you did about how get Vgs.
My question was about how can I get Vbias. I guest that it was created by the Ibias flow. But my question refers that, in case that I don't know the dimensiones (W,L) of M10 yet. I...
Hello jimito13,
I have been checking the tutorial that you have recommend me, it's quite useful, I'm learning how to play with the parameters in order to obtain my goals.
But there is something in the tutorial that I don't understand. In the page 17, it sais that...
I will check all those points then. But why did you say that MN4 and MN5 are not biased?? I see 627mV at the Gate, it should be enough to bias the transistor, isn't it??
Thank you very much for help and info. You has helped me a lot, and I have learn quite much about IC design.
Well, I have been trying to modify some parameters in order to obtain a good output voltage (including the second stage we were talking before). As you can see in the image, I have again a saturated output.
As I told you, I am a rookie in IC design, so I really don't know what should be the...
Ok then, I understand what you meant about Vout offset. I'm going to try to simulated and to correct the offset by myself and if I have some troubles I will let you know.
Related to accuracy control of the gain. I mean which parameters should I take into account in order to modify the gain as I...
Once again, you were right, the input signal were too high.
I did a quickly test circuit to test the differential pair and I didn't think about it. Now it's not getting saturated and it's having a reasonable good gain. (check image)
Anyway I have some others question:
1) I want to use a...
I have been checking all the points you have mentioned.
1) I have used now a current mirror to bias. (Check Image).
2) I was changing some parameters and in the image I upload the parameters where different between both branches, now both are equal.
3) I think that now that I'm using a real...
Sorry, I forgot to show the schematics and the plots. Here they are:
You can see the result of the simulation, as well as the schematic of the differential pair and the schematic used to simulated it.
Hello everybody,
This is my first post in the forum. I hope I can learn as much as possible from all of you, and help you when you need it.
I'm starting right now on IC design, I would like to desing a Two Stages OpAmp. With a differential pair in the first stage.
The differential pair I'm...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
