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My scan-simulation is failing with post-layout netlist with SDF annotation. I'm seeing some timing violations in log file. Could anybody suggest how to debug it.
Also the post-layout STA was clean (e.g. no setup/hold violations in scan-mode), then why during simulation I'm...
Thanks for the inputs.
There is no D1/2/3/9 violation in my design. All the flops are scannable flops. Could anyone explain why there is a huge coverage difference in stuck-at and transition fault (besides the clock frequency)
I'm getting very low transition fault coverage (56%). The tool is cadence's Encounter Test which is pretty new to me. Could anybody suggest how to debug it. What could be the cause of low coverage. The stuck-at fault coverage is around 97%.
Can you share the scripts/steps for transtiotion fault test. I'm running fixed-time test with giving clock frequency info. Is there anything I should give as a input besides pin-assignment file.
I'm new in Encounter Test(cadence tool for ATPG). I want to generate transition fault. I came to know that need to insert the OPCG (On Product Clock Generation) logic during synthesis for this.
Is any other way to generate the transition fault without inserting the OPCG, if yes...
I'm using Cadence's Incisive tool to perfom simulation and code-coverage analysis. My desgin has 2 process FSM modelling style (means combinational and sequential logic defined in two separate process). Problem is not able to do FSM extraction getting below message from log file ...
Thanks narfnarf for detail explanation. You metioned you used ICC, you can help me give some detail about "place_freeze_silicon" command. While modifing the netlist we do not know exact location of spare cells and there is the possibility that may get some timing violations if we choose the...
I want to do metal mask ECO. There are some changes in RTL , I do not want to resynthesis and PnR instead map the new logic using only the spare cells.
Could anybody share what is right way of doing this both at synthesis and layout stage? Is there any automated way ?
I think for uniquify the command is "guide_uniquify" , but did not get why are you giving "guide_reg_merge". Could you please tell how do you know that formality is not able to identify the specific reg, are you manually giving the guidance command or loading the svf file?
You can define the different group paths (command group_path) for those and give the higher values for crictical_range , higher the value of critical_range , the more optimization will be performed by tool. Most of the time it works but you have to check what is the best value for critical range...
Yes DC inserts the cell automatically , but if you mention the specific CG cell you can restrict tool to do not insert higher-driving cells, but it is not mandatory.
DC checks the enable condition (enable pin is the one which decide when to gate clock) , if it passes than it inserts the CG...
Yes those are very old commands. Synopsys has changed DFT commands long time back when they introduced the new DC shell XG mode. But you can translate old dft script by using "db2xg" utility , which should be availabled in DC tool executable location.