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Recent content by dharnishpatel

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    How to link a FPGA design and a NIOSll processor as a sigle FPGA design in DE0 nano.

    Thanks for your reply. :-) I will try in above mentioned way and if it doesn't work then i will try in ur way. I am trying to interface a LCD and a keypad with the NIOSll. For that how should i go with the design of NIOSll. what all things i may require like, clock,I/O,uart. As i know i need to...
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    How to link a FPGA design and a NIOSll processor as a sigle FPGA design in DE0 nano.

    Thanks for your reply. :-) you mean to say i have to create a separate NIOSll project n import my previous design.? can i do the vice-versa,like aft creating a separate NIOSll project n import NIOSll processor as IP on current *.bdf file?
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    How to link a FPGA design and a NIOSll processor as a sigle FPGA design in DE0 nano.

    Hi am trying to integrate a NIOSll processor in my already existing FPGA design so that finally i have a single FPGA solution. I have a signal monitoring unit designed in VHDL and i need to connect the created design to a NIOSll processor for my calculation and displaying the result. I have...
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