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Recent content by dethmaShine

  1. D

    Multiple block RAM modules

    Thanks for the reply. I understood what you said. It's almost the same thing I thought. And yes, I wouldn't mind if you were wrong. Any help is good. Thanks!
  2. D

    Multiple block RAM modules

    Thanks for the reply! I do understand that. In ISE 12.1, it's under tools as Core generator. I have read the documentation concerning Block memory generator. This might not be a good question but I'm thinking about how much Write Width and Write Depth would I need. So supposedly I need 5...
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    Spartan3 vs Spartan 3E

    The best thing would be to consult the Spartan 3 Family Data Sheet and look for the specific differences over there.
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    Multiple block RAM modules

    Could anyone elaborate on this a bit more? Thank you!
  5. D

    Multiple block RAM modules

    I implemented the RAM programmatically using the following code: module memloader(clk50, reset, ml_trans_Address, ml_trans_Data, ml_trans_WriteMe, ml_trans_ReadMe, memdout ); defparam URAM_00.WRITE_MODE = "NO_CHANGE"; //No output unless the write operation finishes //inouts input...
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    Multiple block RAM modules

    I am trying to write a file from the PC to the RAM available on board. I have verified read and write operations to a single BRAM. I have accomplished this through the UsbEpp interface. Now I have a couple of PERL scripts running on my machine which packet the data and provide it to the UsbEpp...
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