Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Recent content by destro98

  1. D

    4 Bit Flash ADC in 180nm Technology

    I am using a Ramp input from 0 to 3.3 volts, Dc voltage as Vref and Power supply Vdd of 3.3 Volts and using current source of 60uA as Bias current.
  2. D

    4 Bit Flash ADC in 180nm Technology

    Thanks for the reply. I want mt ADC to operate from 0.3v to 3v, but my present config cannot operate below 0.5v. What can i do to achieve this?
  3. D

    4 Bit Flash ADC in 180nm Technology

    I didn't get you. Could you explain or help with this rail to rail input stage?
  4. D

    4 Bit Flash ADC in 180nm Technology

    Thanks for the reply. The spikes was due to my Logic gates and it is ok with me. I am having an issue with my ADC, it is not working as i want, i have attached the output graph, you can see in the graph that LSB and One bit in the output are not starting at low voltages. Is there any way to...
  5. D

    4 Bit Flash ADC in 180nm Technology

    I have designed a 4 bit flash ADC in cadence. I have used Two stage op amp as comparator and Fat tree TC to BC Encoder. I am attaching my Output image file. I am getting some unnecessary zeros in my output. Can anyone help me about these drops and how to eliminate them? Thank You. Fat Tree Encoder
  6. D

    [Moved]: Two Stage Comparator for Flash ADC

    I have been designing a Two Stage CMOS Comparator. When i run a transient analysis in Cadence for the circuit in the attachment, it runs only when the input and ref are of same voltage. If the In and Ref are different, i am unable to get the output. This was the test bench This was the...
  7. D

    Current starved VCO cadence design

    Yes OP-amp is the easy one, but we have to design the conversion without the op amp as per our project.
  8. D

    Current starved VCO cadence design

    I want to control the input current, but as it should be voltage controlled, i want to convert voltage to current and give the output current as the input, so that i can vary the voltage and can get the required frequency. Can you help me with how can i design a Vto I converter without using...
  9. D

    Current starved VCO cadence design

    Yes, the input current source changes the oscillator frequency, when i change the current source value the frequency changes, but as it is a voltage controlled oscillators how can i know frequency variations with respect to the voltage variations. How can i know the voltage variation applied for...
  10. D

    Current starved VCO cadence design

    thanks for the help, but i can't understand what do you mean by "running control voltage through in practical circuit" are you saying we should use a DC voltage source as a control voltage?
  11. D

    Current starved VCO cadence design

    Hi, I am trying to design a current starved VCO in cadence, i tried some circuit and it is oscillating, but i don´t know how to vary the input control voltage to get the oscillation frequency from maximum to minimum. i am attaching the png of my design. Any kind of help is appreciated...

Part and Inventory Search

Top