Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Thank you for the feedback , I modified the design more. So now I have only read address and write address. So I use wr_ptr and rd_ptr only as wires connected to wr_addr and rd_addr.
My issue is when rd_en is going high, I see the rd_addr "00A" in my waveform but rd_ptr is "XXX"
I checked the...
Hello,
I modified the design but I am not able to figure out what causes the misbehavior in the design.
Here is the design :
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity circular_buffer is
generic(
DATA_WIDTH : integer := 8;
ADDR_WIDTH ...
I have tried to modify my design and testbench so I tried to divide my design into smaller portions and redesign it . what I have now is only a single write and single read without any empty or full condition but now the write and read pointers are X and the data out stays as XX. Would you...
I modified the design a little bit. I changed the counter so now the counter seems fine, but I still have the following issues :
1. When data_ready flag goes high I need the read operation start reading the data while it keeps writing the rest of the data in the buffer but when the flag goes...
I don't understood your point. I need a counter so when circular buffer writes 188 bytes( a complete packet) then rd_en goes high and the read operation can happen and read that 188 bytes and then rd_en goes low till it sees another data_ready flag and read the next 188 bytes.
As you might seen...
I modified the code. So I have the write operation happening and also I have the flag data_ready that goes high every 188 Bytes(after receiving a complete transport stream packet).
Now I have some other issues:
1. I have a packet counter so it counts the data that is written to the circular...
Hi TrickyDicky,
I modified my design a bit and changed the conditions for memory empty. So now I am able to see in the waveform that the empty signal goes low when the write starts which is correct.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the...
Hi TrickyDicky,
I need to design a circular buffer which write/read data byte by byte. The input of the circular buffer is MPEG transport stream packets and when it receives a complete transport packet (188 bytes) it will tell the rest of the system that data is ready (data_ready flag should go...
Hello dpaul,
Thank you for pointing that out. I fixed that so we read when read enable is 1 and fifo is not empty.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code...
Hi all,
I am trying to design a circular buffer for a project, the project includes couple of modules and the way it should work is to receive a transport packet (188 bytes - which it receives the packet byte by byte) then in circular buffer when I receive 188 byte , the data_ready flag goes up...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
