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Dear All,
I have need your help.
I have a circuit with an analog part and a digital part. Now I am able to simulate in Analog-Mixed Signal Mode in virtuoso, in which the analog part as transistor level, while digital part as a functional view. I'm using only the virtuoso environment.
My...
Good Moorning to all,
I am a newbie in the digital design tool. I have designed a clock divider in VHDL code and i've verified the behavioral using irun and an AMS simulation in Virtuoso. The next step was the conversion from RTL to gate level using RC Compiler.
I have used this simple...
Dear all,
I've a problem during the AMS simulation in virtuoso.
I have created a VHDL module, which generates a PRBS signal and I have imported its in the library manager correctly, because the AMS simulation works well.
There is a problem when i try to connect the output of the VHDL module...
Good Moorning to everybody,
I'm a newbie and I'm a only analog designer.
I've designed a differential receiver and after the conversion (from differential to CMOS) the magnitude of CMOS level is 2.5 V. I've the necessary to convert this digital signal into CMOS level 1.2 V (core level into...
Good Morning to everybody.
I'm training to understand the Back-end process of digital implementation using Encounter.
In order to understand the design flow, I'm training to implements a simple verilog code. But I've a problem, when I want to P&R core, based on two only standard cell, and the...
Good Morning at all,
I've a problem with the ADE L in cadence 6.
I've needed to convert a variable in Design Variable from float to integer. But during the simulation, Spectre returns an error. I've used a a function round(N), where N is my float number. Spectre returns me Function 'round ' is...
Good Moorning at all
I'm a newbie in Cadence IC 6 and now I want to use Ocean to get a Monte Carlo analysis from my schematic.
I've written a simple script in ocean:
monteCarlo(?numIters "3" ?startIter "1" ?analyisisVariation 'mismatch ?sweptParam "None" ?sweptParamVals "27"
?saveData t...
Good Moornig,
I'm a newbie in analog IC design and I have designed a layout for a analog circuit in TSMC 65 nm using Cadence IC 6. Now I want to complete the layout using a pads and sealring. From a Foundry I've downloaded a sealring (gds files) and I've inserted into layout. Regarding a pads...
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